XC1702LPC44C Datasheet PDF - Xilinx
| Part Number | XC1702LPC44C | |
| Description | Configuration PROMs | |
| Manufacturers | Xilinx | |
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R XC1700E and XC1700L Series
Configuration PROMs
DS027 (v3.1) July 5, 2000
08
Features
• One-time programmable (OTP) read-only memory
designed to store configuration bitstreams of Xilinx
FPGA devices
• Simple interface to the FPGA; requires only one user
I/O pin
• Cascadable for storing longer or multiple bitstreams
• Programmable reset polarity (active High or active
Low) for compatibility with different FPGA solutions
• XC17128E/EL, XC17256E/EL, XC1701 and XC1700L
series support fast configuration
• Low-power CMOS Floating Gate process
• XC1700E series are available in 5V and 3.3V versions
• XC1700L series are available in 3.3V only
• Available in compact plastic packages: 8-pin SOIC,
8-pin VOIC, 8-pin PDIP, 20-pin SOIC, 20-pin PLCC,
44-pin PLCC or 44-pin VQFP.
• Programming support by leading programmer
manufacturers.
• Design support using the Xilinx Alliance and
Foundation series software packages.
• Guaranteed 20 year life data retention
Product Specification
Description
The XC1700 family of configuration PROMs provides an
easy-to-use, cost-effective method for storing large Xilinx
FPGA configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising clock edge, data appears on the PROM
DATA output pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.
For device programming, either the Xilinx Alliance or Foun-
dation series development system compiles the FPGA
design file into a standard Hex format, which is then trans-
ferred to most commercial PROM programmers.
VCC VPP GND
RESET/
OE
or
OE/
RESET
CE
CLK
Address Counter
TC
CEO
EPROM
Cell
Matrix
Output
OE
DATA
DS027_01_021500
Figure 1: Simplified Block Diagram (does not show programming circuit)
© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS027 (v3.1) July 5, 2000
Product Specification
www.xilinx.com
1-800-255-7778
1
|
| |
 
R
VCC
XC1700E and XC1700L Series Configuration PROMs
DOUT
FPGA
MODES*
OPTIONAL
Daisy-chained
FPGAs with
Different
configurations
OPTIONAL
Slave FPGAs
with Identical
Configurations
VCC
RESET
RESET
DIN
CCLK
DONE
INIT
3.3V
4.7K
VCC VPP
DATA
CLK PROM
CE CEO
OE/RESET
* For mode pin connections,
refer to the appropriate FPGA data sheet.
(Low Resets the Address Pointer)
CCLK
(Output)
DATA
CLK
CE
Cascaded
Serial
Memory
OE/RESET
DIN
DOUT
(Output)
DS027_02_060100
Figure 2: Master Serial Mode. The one-time-programmable PROM supports automatic loading of configuration programs.
Multiple devices can be cascaded to support additional FPGAs. An early DONE inhibits the PROM data output one CCLK
cycle before the FPGA I/Os become active.
DS027 (v3.1) July 5, 2000
Product Specification
www.xilinx.com
1-800-255-7778
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for XC1702LPC44C electronic component. |
| Information | Total 12 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ XC1702LPC44C.PDF Datasheet ] | |
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