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기능 Configuration PROMs
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XC1702LVQ44I 데이터시트, 핀배열, 회로
0
R XC1700E and XC1700L Series
Configuration PROMs
DS027 (v3.1) July 5, 2000
08
Features
• One-time programmable (OTP) read-only memory
designed to store configuration bitstreams of Xilinx
FPGA devices
• Simple interface to the FPGA; requires only one user
I/O pin
• Cascadable for storing longer or multiple bitstreams
• Programmable reset polarity (active High or active
Low) for compatibility with different FPGA solutions
• XC17128E/EL, XC17256E/EL, XC1701 and XC1700L
series support fast configuration
• Low-power CMOS Floating Gate process
• XC1700E series are available in 5V and 3.3V versions
• XC1700L series are available in 3.3V only
• Available in compact plastic packages: 8-pin SOIC,
8-pin VOIC, 8-pin PDIP, 20-pin SOIC, 20-pin PLCC,
44-pin PLCC or 44-pin VQFP.
• Programming support by leading programmer
manufacturers.
• Design support using the Xilinx Alliance and
Foundation series software packages.
• Guaranteed 20 year life data retention
Product Specification
Description
The XC1700 family of configuration PROMs provides an
easy-to-use, cost-effective method for storing large Xilinx
FPGA configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising clock edge, data appears on the PROM
DATA output pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.
For device programming, either the Xilinx Alliance or Foun-
dation series development system compiles the FPGA
design file into a standard Hex format, which is then trans-
ferred to most commercial PROM programmers.
VCC VPP GND
RESET/
OE
or
OE/
RESET
CE
CLK
Address Counter
TC
CEO
EPROM
Cell
Matrix
Output
OE
DATA
DS027_01_021500
Figure 1: Simplified Block Diagram (does not show programming circuit)
© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS027 (v3.1) July 5, 2000
Product Specification
www.xilinx.com
1-800-255-7778
1




XC1702LVQ44I pdf, 반도체, 판매, 대치품
XC1700E and XC1700L Series Configuration PROMs
Controlling PROMs
Connecting the FPGA device with the PROM.
The DATA output(s) of the of the PROM(s) drives the
DIN input of the lead FPGA device.
The Master FPGA CCLK output drives the CLK input(s)
of the PROM(s).
The CEO output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).
The RESET/OE input of all PROMs is best driven by
the INIT output of the lead FPGA device. This
connection assures that the PROM address counter is
reset before the start of any (re)configuration, even
when a reconfiguration is initiated by a VCC glitch.
Other methodssuch as driving RESET/OE from LDC
or system resetassume the PROM internal
power-on-reset is always in step with the FPGAs
internal power-on-reset. This may not be a safe
assumption.
The PROM CE input can be driven from either the LDC
or DONE pins. Using LDC avoids potential contention
on the DIN pin.
The CE input of the lead (or only) PROM is driven by
the DONE output of the lead FPGA device, provided
that DONE is not permanently grounded. Otherwise,
LDC can be used to drive CE, but must then be
unconditionally High during user operation. CE can
also be permanently tied Low, but this keeps the DATA
output active and causes an unnecessary supply
current of 10 mA maximum.
FPGA Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic Block
(CLB) and their associated interconnections are established
by a configuration program. The program is loaded either
automatically upon power up, or on command, depending
on the state of the three FPGA mode pins. In Master Serial
mode, the FPGA automatically loads the configuration pro-
gram from an external memory. The Xilinx PROMs have
been designed for compatibility with the Master Serial
mode.
Upon power-up or reconfiguration, an FPGA enters the
Master Serial mode whenever all three of the FPGA
mode-select pins are Low (M0=0, M1=0, M2=0). Data is
read from the PROM sequentially on a single data line. Syn-
chronization is provided by the rising edge of the temporary
signal CCLK, which is generated during configuration.
Master Serial Mode provides a simple configuration inter-
face. Only a serial data line and two control lines are
required to configure an FPGA. Data from the PROM is
R
read sequentially, accessed via the internal address and bit
counters which are incremented on every valid rising edge
of CCLK.
If the user-programmable, dual-function DIN pin on the
FPGA is used only for configuration, it must still be held at a
defined level during normal operation. The Xilinx FPGA
families take care of this automatically with an on-chip
default pull-up resistor.
Programming the FPGA With Counters
Unchanged Upon Completion
When multiple FPGA-configurations for a single FPGA are
stored in a PROM, the OE pin should be tied Low. Upon
power-up, the internal address counters are reset and con-
figuration begins with the first program stored in memory.
Since the OE pin is held Low, the address counters are left
unchanged after configuration is complete. Therefore, to
reprogram the FPGA with another program, the DONE line
is pulled Low and configuration begins at the last value of
the address counters.
This method fails if a user applies RESET during the FPGA
configuration process. The FPGA aborts the configuration
and then restarts a new configuration, as intended, but the
PROM does not reset its address counter, since it never
saw a High level on its OE input. The new configuration,
therefore, reads the remaining data in the PROM and inter-
prets it as preamble, length count etc. Since the FPGA is
the master, it issues the necessary number of CCLK pulses,
up to 16 million (224) and DONE goes High. However, the
FPGA configuration will be completely wrong, with potential
contentions inside the FPGA and on its output pins. This
method must, therefore, never be used when there is any
chance of external reset during configuration.
Cascading Configuration PROMs
For multiple FPGAs configured as a daisy-chain, or for
future FPGAs requiring larger configuration memories, cas-
caded PROMs provide additional memory. After the last bit
from the first PROM is read, the next clock signal to the
PROM asserts its CEO output Low and disables its DATA
line. The second PROM recognizes the Low level on its CE
input and enables its DATA output. See Figure 2.
After configuration is complete, the address counters of all
cascaded PROMs are reset if the FPGA RESET pin goes
Low, assuming the PROM reset polarity option has been
inverted.
To reprogram the FPGA with another program, the DONE
line goes Low and configuration begins where the address
counters had stopped. In this case, avoid contention
between DATA and the configured I/O use of DIN.
4
www.xilinx.com
DS027 (v3.1) July 5, 2000
1-800-255-7778
Product Specification

4페이지










XC1702LVQ44I 전자부품, 판매, 대치품
R XC1700E and XC1700L Series Configuration PROMs
XC1701, XC1736E, XC1765E, XC17128E and XC17256E
Absolute Maximum Ratings
Symbol
Description
Conditions Units
VCC Supply voltage relative to GND
0.5 to +7.0
V
VPP Supply voltage relative to GND
0.5 to +12.5
V
VIN Input voltage relative to GND
0.5 to VCC +0.5 V
VTS
TSTG
TSOL
Voltage applied to High-Z output
Storage temperature (ambient)
Maximum soldering temperature (10s @ 1/16 in.)
0.5 to VCC +0.5
65 to +150
+260
V
°C
°C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond those
listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended
periods of time may affect device reliability.
Operating Conditions (5V Supply)
Symbol
Description
Min Max Units
VCC(1)
Supply voltage relative to GND (TA = 0°C to +70°C)
Supply voltage relative to GND (TA = 40°C to +85°C)
Commercial
Industrial
4.750
4.50
5.25
5.50
V
V
Notes:
1. During normal read operation VPP MUST be connect to VCC.
DC Characteristics Over Operating Condition
Symbol
VIH
VIL
VOH
VOL
VOH
VOL
ICCA
ICCS
ICCS
IL
CIN
COUT
Description
High-level input voltage
Low-level input voltage
High-level output voltage (IOH = 4 mA)
Commercial
Low-level output voltage (IOL = +4 mA)
High-level output voltage (IOH = 4 mA)
Industrial
Low-level output voltage (IOL = +4 mA)
Supply current, active mode (at maximum frequency)
Supply current, standby mode
Supply current, standby mode (XC1701)
Input or output leakage current
Input capacitance (VIN = GND, f = 1.0 MHz)
Output capacitance (VIN = GND, f = 1.0 MHz)
Min Max Units
2
VCC
V
0 0.8 V
3.86 -
V
- 0.32 V
3.76 - V
- 0.37 V
- 10 mA
- 50 mA
- 100 mA
10 10 mA
- 10 pF
- 10 pF
DS027 (v3.1) July 5, 2000
Product Specification
www.xilinx.com
1-800-255-7778
7

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