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XC1765DDD8M 데이터시트 PDF




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부품번호 XC1765DDD8M 기능
기능 QPRO Family of XC1700D QML Configuration PROMs
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XC1765DDD8M 데이터시트, 핀배열, 회로
0
R QPRO Family of XC1700D QML
Configuration PROMs
DS070 (v2.1) June 1, 2000
02
Features
• Certified to MIL-PRF-38535 Appendix A QML
(Qualified Manufacturer Listing.)
• Also available under the following Standard Microcircuit
Drawings (SMD): 5962-94717 and 5962-95617.
• Configuration one-time programmable (OTP) read-only
memory designed to store configuration bitstreams of
Xilinx FPGA devices
• On-chip address counter, incremented by each rising
edge on the clock input
• Simple interface to the FPGA requires only one user
I/O pin
• Cascadable for storing longer or multiple bitstreams
• Programmable reset polarity (active High or active
Low) for compatibility with different FPGA solutions
• Low-power CMOS EPROM process
• Available in 5V version only
• Programming support by leading programmer
manufacturers.
• Design support using the Xilinx Alliance and
Foundation series software packages.
Product Specification
Description
The XC1700D QPRO™ family of configuration PROMs pro-
vide an easy-to-use, cost-effective method for storing Xilinx
FPGA configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising clock edge, data appears on the PROM
DATA output pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.
For device programming, either the Xilinx Alliance™ or the
Foundation™ series development systems compiles the
FPGA design file into a standard HEX format which is then
transferred to most commercial PROM programmers.
VCC VPP GND
RESET/
OE
or
OE/
RESET
CE
CLK
Address Counter
TC
CEO
EPROM
Cell
Matrix
Output
OE
DATA
DS027_01_021500
Figure 1: Simplified Block Diagram (does not show programming circuit)
© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS070 (v2.1) June 1, 2000
Product Specification
www.xilinx.com
1-800-255-7778
1




XC1765DDD8M pdf, 반도체, 판매, 대치품
QPRO Family of XC1700D QML Configuration PROMs
Vcc
R
DOUT
FPGA
MODES*
OPTIONAL
Daisy-chained
FPGAs with
Different
configurations
OPTIONAL
Slave FPGAs
with Identical
Configurations
VCC
RESET
RESET
DIN
CCLK
DONE
INIT
3.3V VPP
4.7K
VCC
DATA
VPP
CLK PROM
CE CEO
OE/RESET
* For mode pin connections,
refer to the appropriate FPGA data sheet.
(Low Resets the Address Pointer)
CCLK
(Output)
DATA
CLK
CE
Cascaded
Serial
Memory
OE/RESET
DIN
DOUT
(Output)
DS027_02_052200
Figure 2: Master Serial Mode. The one-time-programmable PROM supports automatic loading of configuration programs.
Multiple devices can be cascaded to support additional FPGAs. An early DONE inhibits the PROM data output one CCLK
cycle before the FPGA I/Os become active.
4
www.xilinx.com
DS070 (v2.1) June 1, 2000
1-800-255-7778
Product Specification

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XC1765DDD8M 전자부품, 판매, 대치품
R QPRO Family of XC1700D QML Configuration PROMs
AC Characteristics Over Operating Condition(1,2)
CE
RESET/OE
CLK
DATA
TSCE
TOE
TCE
TLC THC
TCAC
TSCE
TCYC
THOE
TOH
TDF
THCE
TOH
DS027_03_021500
XC1736D
XC1765D
XC17128D
XC17256D
Symbol
Description
Min Max Min Max
TOE OE to data delay
- 45 - 25
TCE CE to data delay
- 60 - 45
TCAC
TOH
CLK to data delay
Data hold from CE, OE, or CLK(3)
- 150 -
0-0
50
-
TDF CE or OE to data float delay(3,4)
- 50 - 50
TCYC Clock periods
200 - 80 -
TLC CLK Low time(3)
THC CLK High time(3)
100 - 20 -
100 - 20 -
TSCE CE setup time to CLK (to guarantee proper counting)
25 - 20 -
THCE CE hold time to CLK (to guarantee proper counting)
0-0-
THOE OE hold time (guarantees counters are reset)
100 - 20 -
Notes:
1. AC test load = 50 pF
2. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
3. Guaranteed by design, not tested.
4. Float delays are measured with 5 pF AC loads. Transition is measured at ±200mV from steady state active levels.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS070 (v2.1) June 1, 2000
Product Specification
www.xilinx.com
1-800-255-7778
7

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관련 데이터시트

부품번호상세설명 및 기능제조사
XC1765DDD8M

QPRO Family of XC1700D QML Configuration PROMs

Xilinx
Xilinx

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