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XC1800 데이터시트 PDF




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부품번호 XC1800 기능
기능 XC1800 Series of In-System Programmable Configuration PROMs
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XC1800 데이터시트, 핀배열, 회로
d
®
September 17, 1999 (Version 1.3)
0
XC1800 Series of In-System
Programmable Configuration
PROMs
0 6* Preliminary Product Specification
Features
• In-system programmable 3.3V PROMs for configuration
of Xilinx FPGAs
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
• IEEE Std 1149.1 boundary-scan (JTAG) support
• Simple interface to the FPGA; could be configured to
use only one user I/O pin
• Cascadable for storing longer or multiple bitstreams
• Dual configuration modes
- Serial Slow/Fast configuration (up to 15 mHz).
- Parallel
• Low-power advanced CMOS FLASH process
• 5 V tolerant I/O pins accept 5 V, 3.3 V and 2.5 V signals.
• 3.3 V or 2.5 V output capability
• Available in PC20, SO20, PC44 and VQ44 packages.
• Design support using the Xilinx Alliance and
Foundation series software packages.
• JTAG command initiation of standard FPGA
configuration.
Description
Xilinx introduces the XC1800 series of in-system program-
mable configuration PROMs. Initial devices in this 3.3V
family are a 4 megabit, a 2 megabit, a 1 megabit, a 512
Kbit, a 256 Kbit, and a 128 Kbit PROM that provide an
easy-to-use, cost-effective method for re-programming and
storing large Xilinx FPGA or CPLD configuration bit-
streams.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising CCLK, data is available on the PROM
DATA (D0) pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. When the FPGA is in Slave
Serial mode, the PROM and the FPGA are clocked by an
external clock.
When the FPGA is in Express or SelectMAP Mode, an
external oscillator will generate the configuration clock that
drives the PROM and the FPGA. After the rising CCLK
edge, data are available on the PROM’s DATA (D0-D7)
pins. The data will be clocked into the FPGA on the follow-
ing rising edge of the CCLK. Neither Express nor Select-
MAP utilize a Length Count, so a free-running oscillator
may be used. See Figure 5
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family or with
the XC1700L one-time programmable Serial PROM family.
CLK CE
OE/Reset
TCK
TMS
TDI
TDO
Control
and
JTAG
Interface
Data
Address
Memory
Data
Serial
or
Parallel
Interface
CF
Figure 1: XC1800 Series Block Diagram
September 17, 1999 (Version 1.3)
CEO
D0 DATA
(Serial or Parallel
(Express/SelectMAP) Mode)
D1 - D7
Express Mode and
SelectMAP Interface
99020300
1




XC1800 pdf, 반도체, 판매, 대치품
XC1800 Series of In-System Programmable Configuration PROMs
Xilinx FPGAs and Compatible
PROMs
Device
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
XC4002XL
XC4005XL
XC4010XL
XC4013XL/XLA
XC4020XL/XLA
XC4028XL/XLA
XC4036XL/XLA
XC4044XL/XLA
XC4052XL/XLA
XC4062XL/XLA
XC4085XL/XLA
XC40110XV
XC40150XV
XC40200XV
XC40250XV
XCV50
XCV100
XCV150
XCV200
XCV300
XCV400
XCV600
XCV800
XCV1000
Configuration Bits
53,984
95,008
119,840
147,552
178,144
247,968
329,312
422,176
61,100
151,960
283,424
393,632
521,880
668,184
832,528
1,014,928
1,215,368
1,433,864
1,924,992
2,686,136
3,373,448
4,551,056
5,433,888
559,232
781,248
1,041,128
1,335,872
1,751,840
2,546,080
3,608,000
4,715,648
6,127,776
PROM
XC18128
XC18128
XC18128
XC18256
XC18256
XC18256
XC18512
XC18512
XC18128
XC18256
XC18512
XC18512
XC18512
XC1801
XC1801
XC1801
XC1802
XC1802
XC1802
XC1804
XC1804
XC1804 +
XC18512
XC1804 +
XC1802
XC1801
XC1801
XC1801
XC1802
XC1802
XC1804
XC1804
XC1804 +
XC18512
XC1804 +
XC1802
Capacity
Devices
1804
1802
1801
18512
18256
18128
Configuration Bits
4,194,304
2,097,152
1,048,576
524,288
262,144
131,072
R
4 September 17, 1999 (Version 1.3)

4페이지










XC1800 전자부품, 판매, 대치품
R
XC1800 Series of In-System Programmable Configuration PROMs
The USERCODE instruction gives access to a 32-bit user
programmable scratch pad typically used to supply infor-
mation about the devices’s programmed contents. By using
the USERCODE instruction, a user-programmable identifi-
cation code can be shifted our for examination. This code is
loaded into the USERCODE register during programming
of the XC1800 device. If the device is blank or was not
loaded during programming, the USERCODE register will
contain FFFFFFFFh.
XC1800 TAP Characteristics
The XC1800 family performs both in-system programming
and IEEE 1149.1 boundary-scan (JTAG) testing via a single
4-wire Test Access Port (TAP). This simplifies system
designs and allows standard Automatic Test Equipment to
perform both functions. The AC characteristics of the
XC1800 TAP are described as follows.
TAP Timing
Figure 4 shows the timing relationships of the TAP signals.
These TAP timing characteristics are identical for both
boundary-scan and ISP operations.
TCK
TMS
TDI
TDO
TCKMIN
TMSS TMSH
TDIS TDIH
TDOZX
TDOV
TDOXZ
Figure 4: Test Access Port Timing
TAP AC Parameters
Table 5 shows the timing parameters for the TAP wave-
forms shown in Figure 4
Table 5: Test Access Port Timing Parameters (ns)
Symbol
TCKMIN
TMSS
TMSH
TDIS
TDIH
TDOZX
TDOXZ
TDOV
Parameter
TCK Minimum Clock Period
TMS Setup Time
TMS Hold Time
TDI Setup Time
TDI Hold Time
TDO Float to Valid Delay
TDI Valid to Float Delay
TDO Valid Delay
Min Max
100
10
10
15
25
35
35
35
September 17, 1999 (Version 1.3)
7

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부품번호상세설명 및 기능제조사
XC1800

XC1800 Series of In-System Programmable Configuration PROMs

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