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기능 Field Programmable Gate Arrays
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XC5206-4BG225C 데이터시트, 핀배열, 회로
0
R XC5200 Series
Field Programmable Gate Arrays
November 5, 1998 (Version 5.2)
0 7* Product Specification
Features
• Low-cost, register/latch rich, SRAM based
reprogrammable architecture
- 0.5µm three-layer metal CMOS process technology
- 256 to 1936 logic cells (3,000 to 23,000 “gates”)
- Price competitive with Gate Arrays
• System Level Features
- System performance beyond 50 MHz
- 6 levels of interconnect hierarchy
- VersaRingI/O Interface for pin-locking
- Dedicated carry logic for high-speed arithmetic
functions
- Cascade chain for wide input functions
- Built-in IEEE 1149.1 JTAG boundary scan test
circuitry on all I/O pins
- Internal 3-state bussing capability
- Four dedicated low-skew clock or signal distribution
nets
• Versatile I/O and Packaging
- Innovative VersaRingI/O interface provides a high
logic cell to I/O ratio, with up to 244 I/O signals
- Programmable output slew-rate control maximizes
performance and reduces noise
- Zero Flip-Flop hold time for input registers simplifies
system timing
- Independent Output Enables for external bussing
- Footprint compatibility in common packages within
the XC5200 Series and with the XC4000 Series
- Over 150 device/package combinations, including
advanced BGA, TQ, and VQ packaging available
• Fully Supported by Xilinx Development System
- Automatic place and route software
- Wide selection of PC and Workstation platforms
- Over 100 3rd-party Alliance interfaces
- Supported by shrink-wrap Foundation software
Description
The XC5200 Field-Programmable Gate Array Family is
engineered to deliver low cost. Building on experiences
gained with three previous successful SRAM FPGA fami-
lies, the XC5200 family brings a robust feature set to pro-
grammable logic design. The VersaBlocklogic module,
the VersaRing I/O interface, and a rich hierarchy of inter-
connect resources combine to enhance design flexibility
and reduce time-to-market. Complete support for the
XC5200 family is delivered through the familiar Xilinx soft-
ware environment. The XC5200 family is fully supported on
popular workstation and PC platforms. Popular design
entry methods are fully supported, including ABEL, sche-
matic capture, VHDL, and Verilog HDL synthesis. Design-
ers utilizing logic synthesis can use their existing tools to
design with the XC5200 devices.
.
Table 1: XC5200 Field-Programmable Gate Array Family Members
Device
Logic Cells
Max Logic Gates
Typical Gate Range
VersaBlock Array
CLBs
Flip-Flops
I/Os
TBUFs per Longline
XC5202
256
3,000
2,000 - 3,000
8x8
64
256
84
10
XC5204
XC5206
XC5210
XC5215
480
784
1,296
1,936
6,000
10,000
16,000
23,000
4,000 - 6,000 6,000 - 10,000 10,000 - 16,000 15,000 - 23,000
10 x 12
14 x 14
18 x 18
22 x 22
120 196 324 484
480
784
1,296
1,936
124 148 196 244
14 16 20 24
7
November 5, 1998 (Version 5.2)
7-83




XC5206-4BG225C pdf, 반도체, 판매, 대치품
XC5200 Series Field Programmable Gate Arrays
R
The XC5200 CLB consists of four LCs, as shown in
Figure 4. Each CLB has 20 independent inputs and 12
independent outputs. The top and bottom pairs of LCs can
be configured to implement 5-input functions. The chal-
lenge of FPGA implementation software has always been
to maximize the usage of logic resources. The XC5200
family addresses this issue by surrounding each CLB with
two types of local interconnect — the Local Interconnect
Matrix (LIM) and direct connects. These two interconnect
resources, combined with the CLB, form the VersaBlock,
represented in Figure 2.
LC3
DI
F4
F3
F2 F
F1
CO
DO
DQ
FD
X
LC2
DI
F4
F3
F2 F
F1
DO
DQ
FD
X
LC1
DI
F4
F3
F2 F
F1
DO
DQ
FD
X
LC0
DI
F4
F3
F2 F
F1
CI
DO
DQ
FD
CE CK CLR
X
X4957
Figure 4: Configurable Logic Block
The LIM provides 100% connectivity of the inputs and out-
puts of each LC in a given CLB. The benefit of the LIM is
that no general routing resources are required to connect
feedback paths within a CLB. The LIM connects to the
GRM via 24 bidirectional nodes.
The direct connects allow immediate connections to neigh-
boring CLBs, once again without using any of the general
interconnect. These two layers of local routing resource
improve the granularity of the architecture, effectively mak-
ing the XC5200 family a “sea of logic cells.” Each
Versa-Block has four 3-state buffers that share a common
enable line and directly drive horizontal and vertical Lon-
glines, creating robust on-chip bussing capability. The
VersaBlock allows fast, local implementation of logic func-
tions, effectively implementing user designs in a hierarchi-
cal fashion. These resources also minimize local routing
congestion and improve the efficiency of the general inter-
connect, which is used for connecting larger groups of
logic. It is this combination of both fine-grain and
coarse-grain architecture attributes that maximize logic uti-
lization in the XC5200 family. This symmetrical structure
takes full advantage of the third metal layer, freeing the
placement software to pack user logic optimally with mini-
mal routing restrictions.
VersaRing I/O Interface
The interface between the IOBs and core logic has been
redesigned in the XC5200 family. The IOBs are completely
decoupled from the core logic. The XC5200 IOBs contain
dedicated boundary-scan logic for added board-level test-
ability, but do not include input or output registers. This
approach allows a maximum number of IOBs to be placed
around the device, improving the I/O-to-gate ratio and
decreasing the cost per I/O. A “freeway” of interconnect
cells surrounding the device forms the VersaRing, which
provides connections from the IOBs to the internal logic.
These incremental routing resources provide abundant
connections from each IOB to the nearest VersaBlock, in
addition to Longline connections surrounding the device.
The VersaRing eliminates the historic trade-off between
high logic utilization and pin placement flexibility. These
incremental edge resources give users increased flexibility
in preassigning (i.e., locking) I/O pins before completing
their logic designs. This ability accelerates time-to-market,
since PCBs and other system components can be manu-
factured concurrent with the logic design.
General Routing Matrix
The GRM is functionally similar to the switch matrices
found in other architectures, but it is novel in its tight cou-
pling to the logic resources contained in the VersaBlocks.
Advanced simulation tools were used during the develop-
ment of the XC5200 architecture to determine the optimal
level of routing resources required. The XC5200 family
contains six levels of interconnect hierarchy — a series of
7-86
November 5, 1998 (Version 5.2)

4페이지










XC5206-4BG225C 전자부품, 판매, 대치품
R
XC5200 Series Field Programmable Gate Arrays
tomized RPMs, freeing the designer from the need to
become an expert on architectures.
cascade out
CO
DI
A15 F4
A14 F3
A13 F2 AND
A12 F1
CY_MUX
DI
A11 F4
A10 F3
A9 F2 AND
A8 F1
CY_MUX
DI
A7 F4
A6 F3
A5 F2 AND
A4 F1
CY_MUX
DI
A3 F4
A2 F3
A1 F2 AND
A0 F1
CY_MUX
CI
cascade in
DO
DQ
FD
X
LC3
DO
DQ
FD
X
LC2
DO
DQ
FD
X
LC1
DO
DQ
FD
CE CK
X
CLR LC0
out
CY_MUX
F=0 Initialization of
carry chain (One Logic Cell)
X5708
Figure 7: XC5200 CY_MUX Used for Decoder Cascade
Logic
Cascade Function
Each CY_MUX can be connected to the CY_MUX in the
adjacent LC to provide cascadable decode logic. Figure 7
illustrates how the 4-input function generators can be con-
figured to take advantage of these four cascaded
CY_MUXes. Note that AND and OR cascading are specific
cases of a general decode. In AND cascading all bits are
decoded equal to logic one, while in OR cascading all bits
are decoded equal to logic zero. The flexibility of the LUT
achieves this result. The XC5200 library contains gate
macros designed to take advantage of this function.
CLB Flip-Flops and Latches
The CLB can pass the combinatorial output(s) to the inter-
connect network, but can also store the combinatorial
results or other incoming data in flip-flops, and connect
their outputs to the interconnect network as well. The CLB
storage elements can also be configured as latches.
Table 3: CLB Storage Element Functionality
(active rising edge is shown)
Mode
CK CE CLR D
Q
Power-Up or
GR
X
X
X
X
0
XX1X0
Flip-Flop __/
1*
0*
D
D
0 X 0* X Q
Latch
1 1* 0* X Q
0 1* 0* D D
Both
X 0 0* X Q
Legend:
X
__/
0*
1*
Don’t care
Rising edge
Input is Low or unconnected (default value)
Input is High or unconnected (default value)
Data Inputs and Outputs
The source of a storage element data input is programma-
ble. It is driven by the function F, or by the Direct In (DI)
block input. The flip-flops or latches drive the Q CLB out-
puts.
Four fast feed-through paths from DI to DO are available,
as shown in Figure 4. This bypass is sometimes used by
the automated router to repower internal signals. In addi-
tion to the storage element (Q) and direct (DO) outputs,
there is a combinatorial output (X) that is always sourced
by the Lookup Table.
The four edge-triggered D-type flip-flops or level-sensitive
latches have common clock (CK) and clock enable (CE)
inputs. Any of the clock inputs can also be permanently
enabled. Storage element functionality is described in
Table 3.
Clock Input
The flip-flops can be triggered on either the rising or falling
clock edge. The clock pin is shared by all four storage ele-
ments with individual polarity control. Any inverter placed
on the clock input is automatically absorbed into the CLB.
Clock Enable
The clock enable signal (CE) is active High. The CE pin is
shared by the four storage elements. If left unconnected
for any, the clock enable for that storage element defaults
to the active state. CE is not invertible within the CLB.
Clear
An asynchronous storage element input (CLR) can be used
to reset all four flip-flops or latches in the CLB. This input
7
November 5, 1998 (Version 5.2)
7-89

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Field Programmable Gate Arrays

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