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부품번호 | XC95216-15PQ160C 기능 |
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기능 | XC95216 In-System Programmable CPLD | ||
제조업체 | Xilinx | ||
로고 | |||
전체 10 페이지수
1
XC95216 In-System Programmable
CPLD
August 21, 2001 (Version 3.1)
1 0* Product Specification
Features
• 10 ns pin-to-pin logic delays on all pins
• fCNT to 111 MHz
• 216 macrocells with 4800 usable gates
• Up to 166 user I/O pins
• 5 V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset signals
• Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
• Programmable power reduction mode in each
macrocell
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design protection
• High-drive 24 mA outputs
• 3.3 V or 5 V I/O capability
• Advanced CMOS 5V FastFLASH technology
• Supports parallel programming of more than one
XC9500 concurrently
• Available in 160-pin PQFP, 352-pin BGA, and 208-pin
HQFP packages
Description
The XC95216 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of twelve
36V18 Function Blocks, providing 4,800 usable gates with
propagation delays of 10 ns. See Figure 2 for the architec-
ture overview.
Power Management
Power dissipation can be reduced in the XC95216 by con-
figuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
ICC (mA) =
MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical calculation for the XC95216
device.
600
400
(360)
200
High Performance
Low Power
(500)
(340)
0 50 100
Clock Frequency (MHz)
X5918
Figure 1: Typical ICC vs. Frequency For XC95216
August 21, 2001 (Version 3.1)
1
XC95216 In-System Programmable CPLD
DC Characteristics Over Recommended Operating Conditions
Symbol
VOH
Parameter
Output high voltage for 5 V operation
Output high voltage for 3.3 V operation
VOL Output low voltage for 5 V operation
Output low voltage for 3.3 V operation
IIL Input leakage current
IIH I/O high-Z leakage current
CIN I/O capacitance
ICC Operating Supply Current
(low power mode, active)
Test Conditions
IOH = -4.0 mA
VCC = Min
IOH = -3.2 mA
VCC = Min
IOL = 24 mA
VCC = Min
IOL = 10 mA
VCC = Min
VCC = Max
VIN = GND or VCC
VCC = Max
VIN = GND or VCC
VIN = GND
f = 1.0 MHz
VI = GND, No load
f = 1.0 MHz
Min Max
2.4
2.4
0.5
0.4
±10.0
±10.0
10.0
200 (typ)
R
Units
V
V
V
V
µA
µA
pF
ma
AC Characteristics
Symbol
Parameter
XC95216-10 XC95216-15 XC95216-20
Units
Min Max Min Max Min Max
tPD I/O to output valid
tSU I/O setup time before GCK
tH I/O hold time after GCK
tCO GCK to output valid
fCNT1
16-bit counter frequency
fSYSTEM 2 Multiple FB internal operating frequency
tPSU
I/O setup time before p-term clock input
tPH I/O hold time after p-term clock input
tPCO
P-term clock to output valid
tOE GTS to output valid
tOD GTS to output disable
tPOE
Product term OE to output enabled
tPOD
Product term OE to output disabled
tWLH
GCK pulse width (High or Low)
10.0
15.0
20.0 ns
6.0 8.0 10.0 ns
0.0 0.0 0.0 ns
6.0 8.0 10.0 ns
111.1
95.2
83.3
MHz
66.7
55.6
50.0
MHz
2.0 4.0 4.0 ns
4.0 4.0 6.0 ns
10.0
12.0
16.0 ns
6.0
11.0
16.0 ns
6.0
11.0
16.0 ns
10.0
14.0
18.0 ns
10.0
14.0
18.0 ns
4.5 5.5 5.5 ns
Note: 1. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable.
fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG.
2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs.
4 August 21, 2001 (Version 3.1)
4페이지 R
XC95216 In-System Programmable CPLD
XC95216 I/O Pins (continued)
Function
Block
Macrocell
PQ160
5 1–
5 2 45
5 3 47
5 4–
5 5 48
5 6 49
5 7–
5 8 50
5 9 52
5 10 –
5 11 53
5 12 54
5 13 –
5 14 55
5 15 56
5 16 –
5 17 57
5 18 –
6 1–
6 2 140
6 3 142
6 4–
6 5 143
6 6 144
6 7–
6 8 145
6 9 146
6 10 –
6 11 147
6 12 148
6 13 –
6 14 149
6 15 150
6 16 –
6 17 151
6 18 –
HQ208
–
58
60
41
61
63
–
64
70
109
71
72
–
73
74
40
75
–
–
180
182
208
185
186
–
187
188
183
191
192
–
193
194
169
197
–
BG352
–
AE22
AE21
W25
AF21
AD19
–
AE20
AF18
AD1
AE17
AE16
–
AF16
AE14
Y26
AF14
–
–
A12
A13
D22
C14
A15
–
B15
C15
B14
A16
C16
–
C17
B18
D9
C19
–
BScan
Order
429
426
423
420
417
414
411
408
405
402
399
396
393
390
387
384
381
378
375
372
369
366
363
360
357
354
351
348
345
342
339
336
333
330
327
324
Notes
Function
Block
Macrocell
PQ160
7 1–
7 2 58
7 3 59
7 4–
7 5 60
7 6 62
7 7–
7 8 63
7 9 64
7 10 –
7 11 65
7 12 66
7 13 –
7 14 67
7 15 68
7 16 –
7 17 69
7 18 –
8 1–
8 2 126
8 3 128
8 4–
8 5 129
8 6 130
8 7–
8 8 131
8 9 132
8 10 –
8 11 133
8 12 134
8 13 –
8 14 135
8 15 138
8 16 –
8 17 139
8 18 –
HQ208
–
76
77
54
78
82
–
83
84
91
85
86
–
87
88
48
89
–
–
162
164
143
166
167
–
170
171
195
173
174
–
175
178
189
179
–
BG352
–
AE13
AC13
AE24
AD13
AD12
–
AC12
AF11
AD8
AE11
AE9
–
AD9
AC10
AC26
AF7
–
–
B5
B6
J1
D8
B7
–
C10
B9
A20
A9
D11
–
B11
C12
D15
B12
–
BScan
Order
321
318
315
312
309
306
303
300
297
294
291
288
285
282
279
276
273
270
267
264
261
258
255
252
249
246
243
240
237
234
231
228
225
222
219
216
Notes
August 21, 2001 (Version 3.1)
7
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부품번호 | 상세설명 및 기능 | 제조사 |
XC95216-15PQ160C | XC95216 In-System Programmable CPLD | Xilinx |
XC95216-15PQ160I | XC95216 In-System Programmable CPLD | Xilinx |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |