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XC9536-5CS48C 데이터시트 PDF




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부품번호 XC9536-5CS48C 기능
기능 XC9536 In-System Programmable CPLD
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XC9536-5CS48C 데이터시트, 핀배열, 회로
9
®
1
XC9536 In-System Programmable
CPLD
December 4, 1998 (Version 5.0)
1 1* Product Specification
Features
• 5 ns pin-to-pin logic delays on all pins
• fCNT to 100 MHz
• 36 macrocells with 800 usable gates
• Up to 34 user I/O pins
• 5 V in-system programmable (ISP)
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset signals
• Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
• Programmable power reduction mode in each
macrocell
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design protection
• High-drive 24 mA outputs
• 3.3 V or 5 V I/O capability
• Advanced CMOS 5V FastFLASH technology
• Supports parallel programming of more than one
XC9500 concurrently
• Available in 44-pin PLCC, 44-pin VQFP, and 48-pin
CSP packages
Description
The XC9536 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of two
36V18 Function Blocks, providing 800 usable gates with
propagation delays of 5 ns. See Figure 2 for the architec-
ture overview.
Power Management
Power dissipation can be reduced in the XC9536 by config-
uring macrocells to standard or low-power modes of opera-
tion. Unused macrocells are turned off to minimize power
dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
ICC (mA) =
MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical calculation for the XC9536 device.
High Performance
(50)
Low Power
(30)
(83)
(50)
0 50 100
Clock Frequency (MHz)
X5920
Figure 1: Typical ICC vs. Frequency For XC9536
December 4, 1998 (Version 5.0)
1




XC9536-5CS48C pdf, 반도체, 판매, 대치품
XC9536 In-System Programmable CPLD
DC Characteristics Over Recommended Operating Conditions
Symbol
VOH
VOL
IIL
IIH
CIN
ICC
Parameter
Test Conditions
Output high voltage for 5 V operation IOH = -4.0 mA
VCC = Min
Output high voltage for 3.3 V operation IOH = -3.2 mA
VCC = Min
Output low voltage for 5 V operation IOL = 24 mA
VCC = Min
Output low voltage for 3.3 V operation IOL = 10 mA
VCC = Min
Input leakage current
VCC = Max
VIN = GND or VCC
I/O high-Z leakage current
VCC = Max
VIN = GND or VCC
I/O capacitance
VIN = GND
f = 1.0 MHz
Operating Supply Current
(low power mode, active)
VI = GND, No load
f = 1.0 MHz
Min Max
2.4
2.4
0.5
0.4
±10.0
±10.0
10.0
30 (Typ)
Units
V
V
V
V
µA
µA
pF
mA
AC Characteristics
Symbol
Parameter
XC9536-5 XC9536-6 XC9536-7 XC9536-10 XC9536-15
Units
Min Max Min Max Min Max Min Max Min Max
tPD I/O to output valid
5.0 6.0 7.5 10.0 15.0 ns
tSU I/O setup time before GCK
3.5 3.5 4.5 6.0 8.0
ns
tH I/O hold time after GCK
0.0 0.0 0.0 0.0 0.0
ns
tCO GCK to output valid
4.0 4.0 4.5 6.0 8.0 ns
fCNT1
16-bit counter frequency
100.0
100.0
83.3
66.7
55.6
MHz
fSYSTEM 2 Multiple FB internal operating frequency 100.0
100.0
83.3
66.7
55.6
MHz
tPSU
I/O setup time before p-term clock input 0.5
0.5
0.5
2.0
4.0
ns
tPH I/O hold time after p-term clock input 3.0 3.0 4.0 4.0 4.0
ns
tPCO
P-term clock to output valid
7.0
7.0
8.5
10.0
12.0 ns
tOE GTS to output valid
5.0 5.0 5.5 6.0 11.0 ns
tOD GTS to output disable
5.0 5.0 5.5 6.0 11.0 ns
tPOE
Product term OE to output enabled
9.0 9.0 9.5 10.0 14.0 ns
tPOD
Product term OE to output disabled
9.0 9.0 9.5 10.0 14.0 ns
tWLH
GCK pulse width (High or Low)
4.0 4.0 4.0 4.5 5.5
ns
Note: 1. fCNT is the fastest 16-bit counter frequency available.
fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG.
2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs.
4 December 4, 1998 (Version 5.0)

4페이지










XC9536-5CS48C 전자부품, 판매, 대치품
XC9536 In-System Programmable CPLD
Ordering Information
XC9536 -5 PC 44 C
Device Type
Speed
Temperature Range
Number of Pins
Package Type
Speed Options
-15
-10
-7
-6
-5
15 ns pin-to-pin delay
10 ns pin-to-pin delay
7.5 ns pin-to-pin delay
6 ns pin-to-pin delay
5 ns pin-to-pin delay
Packaging Options
PC44 44-Pin Plastic Leaded Chip Carrier (PLCC)
VQ44 44-Pin Thin Quad Pack (VQFP)
CS48 48-Pin Chip Scale Package (CSP)
Temperature Options
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
Component Availability
Pins
Type
Code
XC9536
44
Plastic
Plastic
PLCC
VQFP
PC44
VQ44
–15 C,I
C,I
–10 C,I
C,I
–7 C,I
C,I
–6 C
C
–5 C
C
48
Plastic
CSP
CS48
-
C
C
-
C
C = Commercial (0°C to +70°C), I = Industrial (–40°C to +85°C)
Revision Control
Date
6/3/98
11/2/98
12/04/98
Reason
Revise datasheet to reflect new CSP package pinouts & ordering code.
Revise datasheet to reflect new AC characteristics and Internal Timing Parameters.
Revise datasheet to remove PCI compliancy statement and remove tLF.
December 4, 1998 (Version 5.0)
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