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XCR3032XL-10PC44I 데이터시트 PDF




Xilinx에서 제조한 전자 부품 XCR3032XL-10PC44I은 전자 산업 및 응용 분야에서
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부품번호 XCR3032XL-10PC44I 기능
기능 XCR3032XL 32 Macrocell CPLD
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XCR3032XL-10PC44I 데이터시트, 핀배열, 회로
0
R XCR3032XL 32 Macrocell CPLD
DS023 (v1.5) January 8, 2002
0 14 Preliminary Product Specification
Features
• Lowest power 32 macrocell CPLD
• 5.0 ns pin-to-pin logic delays
• System frequencies up to 200 MHz
• 32 macrocells with 750 usable gates
• Available in small footprint packages
- 48-ball CS BGA (36 user I/O pins)
- 44-pin VQFP (36 user I/O)
- 44-pin PLCC (36 user I/O)
• Optimized for 3.3V systems
- Ultra-low power operation
- 5V tolerant I/O pins with 3.3V core supply
- Advanced 0.35 micron five layer metal EEPROM
process
- Fast Zero Power™ (FZP) CMOS design
technology
• Advanced system features
- In-system programming
- Input registers
- Predictable timing model
- Up to 23 available clocks per function block
- Excellent pin retention during design changes
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
- Four global clocks
- Eight product term control terms per function block
• Fast ISP programming times
• Port Enable pin for dual function of JTAG ISP pins
• 2.7V to 3.6V supply voltage at industrial temperature
range
• Programmable slew rate control per macrocell
• Security bit prevents unauthorized access
• Refer to XPLA3 family data sheet (DS012) for
architecture description
Table 1: ICC vs. Frequency (VCC = 3.3V, 25°C)
Frequency (MHz)
01
Typical ICC (mA)
0.02 0.13
5
0.54
Description
The XCR3032XL is a 3.3V, 32-macrocell CPLD targeted at
power sensitive designs that require leading edge program-
mable logic solutions. A total of two function blocks provide
750 usable gates. Pin-to-pin propagation delays are 5.0 ns
with a maximum system frequency of 200 MHz.
TotalCMOS Design Technique for Fast
Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technol-
ogy and design technique. Xilinx employs a cascade of
CMOS gates to implement its sum of products instead of
the traditional sense amp approach. This CMOS gate imple-
mentation allows Xilinx to offer CPLDs that are both high
performance and low power, breaking the paradigm that to
have low power, you must have low performance. Refer to
Figure 1 and Table 1 showing the ICC vs. Frequency of our
XCR3032XL TotalCMOS CPLD (data taken with two
resetable up/down, 16-bit counters at 3.3V, 25°C).
20
15
10
5
0
0 20 40 60 80 100 120 140 160 180 200
Frequency (MHz)
DS023_01_080101
Figure 1: ICC vs. Frequency at VCC = 3.3V, 25°C
10 20
1.06 2.09
50 100 200
5.2 10.26 20.3
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS023 (v1.5) January 8, 2002
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
1




XCR3032XL-10PC44I pdf, 반도체, 판매, 대치품
XCR3032XL 32 Macrocell CPLD
R
Internal Timing Parameters(1,2)
-5
Symbol
Parameter
Min. Max.
Buffer Delays
TIN Input buffer delay
TFIN
Fast Input buffer delay
TGCK
Global Clock buffer delay
TOUT
Output buffer delay
TEN Output buffer enable/disable delay
Internal Register and Combinatorial Delays
- 0.7
- 2.2
- 0.7
- 1.8
- 4.5
TLDI Latch transparent delay
TSUI
Register setup time
THI Register hold time
TECSU
Register clock enable setup time
TECHO
Register clock enable hold time
TCOI
Register clock to output delay
TAOI Register async. S/R to output delay
TRAI
Register async. recovery
TLOGI1 Internal logic delay (single p-term)
TLOGI2 Internal logic delay (PLA OR term)
Feedback Delays
- 1.3
1.0 -
0.3 -
2.0 -
3.0 -
- 1.0
- 2.0
- 3.5
- 2.0
- 2.5
TF ZIA delay
Time Adders
- 0.5
TLOGI3
Fold-back NAND delay
- 2.0
TUDA
Universal delay
- 1.2
TSLEW
Slew rate limited delay
- 4.0
Notes:
1. These parameters guaranteed by design and characterization, not testing.
2. See XPLA3 family data sheet (DS012) for timing model.
-7
Min. Max.
-10
Min. Max.
Unit
- 1.6 - 2.2 ns
- 3.0 - 3.1 ns
- 1.0 - 1.3 ns
- 2.7 - 3.6 ns
- 5.0 - 5.7 ns
- 1.6 - 2.0 ns
1.0 - 1.2 -
ns
0.5 - 0.7 - ns
2.5 - 3.0 -
ns
4.5 - 5.5 -
ns
- 1.3 - 1.6 ns
- 2.3 - 2.1 ns
- 5.0 - 6.0 ns
- 2.7 - 3.3 ns
- 3.2 - 4.2 ns
- 2.9 - 3.5 ns
- 2.5 - 3.0 ns
- 2.0 - 2.5 ns
- 5.0 - 6.0 ns
4
www.xilinx.com
DS023 (v1.5) January 8, 2002
1-800-255-7778
Preliminary Product Specification

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XCR3032XL-10PC44I 전자부품, 판매, 대치품
R
Ordering Information
Example: XCR3032XL -5 VQ 44 C
Device Type
Speed Grade
XCR3032XL 32 Macrocell CPLD
Temperature Range
Number of Pins
Package Type
Device Ordering Options
Speed
-10 10 ns pin-to-pin
delay
-7 7.5 ns pin-to-pin
delay
-5 5 ns pin-to-pin delay
PC44
VQ44
CS48
Package
44-pin Plastic Lead Chip Carrier
(PLCC)
44-pin Very Thin Quad Flat Pack
(VQFP)
48-ball Chip Scale Package
Temperature
C = Commercial
I = Industrial
TA = 0°C to +70°C
VCC = 3.0V to 3.6V
TA = 40°C to +85°C
VCC = 2.7V to 3.6V
Component Availability
Pins
Type
Code
XCR3032XL
-5
-7
-10
44
Plastic PLCC
PC44
C
C,I
C, I
44
Plastic VQFP
VQ44
C
C,I
C, I
48
Plastic BGA
CS48
C
C,I
C, I
DS023 (v1.5) January 8, 2002
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
7

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