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부품번호 XCR3064XL-6VQ100I 기능
기능 XCR3064XL 64 Macrocell CPLD
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XCR3064XL-6VQ100I 데이터시트, 핀배열, 회로
0
R XCR3064XL 64 Macrocell CPLD
DS017 (v1.6) January 8, 2002
0 14 Product Specification
Features
• Lowest power 64 macrocell CPLD
• 6.0 ns pin-to-pin logic delays
• System frequencies up to 145 MHz
• 64 macrocells with 1,500 usable gates
• Available in small footprint packages
- 44-pin PLCC (36 user I/O pins)
- 44-pin VQFP (36 user I/O pins)
- 48-ball CS BGA (40 user I/O pins)
- 56-ball CP BGA (48 user I/O pins)
- 100-pin VQFP (68 user I/O pins)
• Optimized for 3.3V systems
- Ultra-low power operation
- 5V tolerant I/O pins with 3.3V core supply
- Advanced 0.35 micron five layer metal EEPROM
process
- Fast Zero Power™ (FZP) CMOS design
technology
• Advanced system features
- In-system programming
- Input registers
- Predictable timing model
- Up to 23 available clocks per function block
- Excellent pin retention during design changes
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
- Four global clocks
- Eight product term control terms per function block
• Fast ISP programming times
• Port Enable pin for dual function of JTAG ISP pins
• 2.7V to 3.6V supply voltage at industrial temperature
range
• Programmable slew rate control per macrocell
• Security bit prevents unauthorized access
• Refer to XPLA3 family data sheet (DS012) for
architecture description
Description
The XCR3064XL is a 3.3V, 64-macrocell CPLD targeted at
power sensitive designs that require leading edge program-
mable logic solutions. A total of four function blocks provide
1,500 usable gates. Pin-to-pin propagation delays are
6.0 ns with a maximum system frequency of 145 MHz.
TotalCMOS Design Technique for Fast
Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technol-
ogy and design technique. Xilinx employs a cascade of
CMOS gates to implement its sum of products instead of
the traditional sense amp approach. This CMOS gate imple-
mentation allows Xilinx to offer CPLDs that are both high
performance and low power, breaking the paradigm that to
have low power, you must have low performance. Refer to
Figure 1 and Table 1 showing the ICC vs. Frequency of our
XCR3064XL TotalCMOS CPLD (data taken with four
resetable up/down, 16-bit counters at 3.3V, 25°C).
35.0
30.0
25.0
20.0
15.0
10.0
5.0
0.0
0 20 40 60 80 100 120 140
Frequency (MHz)
DS017_01_102401
Figure 1: ICC vs. Frequency at VCC = 3.3V, 25°C
Table 1: ICC vs. Frequency (VCC = 3.3V, 25°C)
Frequency (MHz) 0 1 5 10 20 40 60 80 100 120 140
Typical ICC (mA)
0
0.2 1.0 2.0 3.9 7.6 11.3 14.8 18.5 22.1 25.6
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS017 (v1.6) January 8, 2002
Product Specification
www.xilinx.com
1-800-255-7778
1




XCR3064XL-6VQ100I pdf, 반도체, 판매, 대치품
XCR3064XL 64 Macrocell CPLD
Internal Timing Parameters(2)
-6
Symbol
Parameter
Min. Max.
Buffer Delays
TIN Input buffer delay
TFIN
Fast Input buffer delay
TGCK
Global Clock buffer delay
TOUT
Output buffer delay
TEN Output buffer enable/disable delay
Internal Register and Combinatorial Delays
- 1.3
- 2.3
- 0.8
- 2.2
- 4.2
TLDI Latch transparent delay
TSUI
Register setup time
THI Register hold time
TECSU
Register clock enable setup time
TECHO
Register clock enable hold time
TCOI
Register clock to output delay
TAOI Register async. S/R to output delay
TRAI
Register async. recovery
TLOGI1 Internal logic delay (single p-term)
TLOGI2 Internal logic delay (PLA OR term)
Feedback Delays
- 1.3
1.0 -
0.3 -
2.0 -
3.0 -
- 1.0
- 2.5
- 4.0
- 2.0
- 2.5
TF ZIA delay
Time Adders
- 2.4
TLOGI3
Fold-back NAND delay
- 6.0
TUDA
Universal delay
- 1.5
TSLEW
Slew rate limited delay
- 4.0
Notes:
1. These parameters guaranteed by design and/or characterization, not testing.
2. See XPLA3 family data sheet (DS012) for timing model.
R
-7
Min. Max.
-10
Min. Max.
Unit
- 1.6 - 2.2 ns
- 3.0 - 3.1 ns
- 1.0 - 1.3 ns
- 2.7 - 3.6 ns
- 5.0 - 5.7 ns
- 1.6 - 2.0
1.0 - 1.2 -
ns
0.5 - 0.7 - ns
2.5 - 3.0 -
ns
4.5 - 5.5 -
ns
- 1.3 - 1.6 ns
- 2.3 - 2.1 ns
- 5.0 - 6.0 ns
- 2.7 - 3.3 ns
- 3.2 - 4.2 ns
- 2.9 - 3.5 ns
- 7.5 - 9.5 ns
- 2.0 - 2.5 ns
- 5.0 - 6.0 ns
4
www.xilinx.com
DS017 (v1.6) January 8, 2002
1-800-255-7778
Product Specification

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XCR3064XL-6VQ100I 전자부품, 판매, 대치품
R XCR3064XL 64 Macrocell CPLD
Table 4: XCR3064XL Global, JTAG, Port Enable, Power, and No connect Pins
Pin Type
PC44
VQ44
CS48
CP56
VQ100
IN0 / CLK0
2
40 A3 C5 90
IN1 / CLK1
1
39 B4 C6 89
IN2 / CLK2
44
38
A4
C7
88
IN3 / CLK3
43
37
B5
A6
87
TCK
32
26
E5 F10 62
TDI 7
1 B1 C1 4
TDO
38
32
B7 C10 73
TMS
13
7
D2 G1 15
PORT_EN
10(1)
4(1)
C3(1)
E1(1)
11(1)
VCC 3, 15, 23, 35 9, 17, 29, 41 B3, C7, E2, A4, D10, H1, 3, 18, 34, 39,
G4 H5 51, 66, 82, 91
GND
22, 30, 42
16, 24, 36
A5, E3, E6
A7, G10, K6 26, 38, 43, 59,
74, 86, 95
No Connects
-
-
-
- 1, 2, 5, 7, 22,
24, 27, 28, 49,
50, 53, 55, 70,
72, 77, 78
Notes:
1. Port Enable is brought High to enable JTAG pins when JTAG pins are used as I/O. See family data sheet
(DS012) for more information.
DS017 (v1.6) January 8, 2002
Product Specification
www.xilinx.com
1-800-255-7778
7

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