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XCS05XL PDF 데이터시트 ( Data , Function )

부품번호 XCS05XL 기능
기능 Spartan and Spartan-XL Families Field Programmable Gate Arrays
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XCS05XL 데이터시트, 핀배열, 회로
0
R Spartan and Spartan-XL Families
Field Programmable Gate Arrays
DS060 (v1.6) September 19, 2001
0 0 Product Specification
Introduction
The Spartanand the Spartan-XL families are a high-vol-
ume production FPGA solution that delivers all the key
requirements for ASIC replacement up to 40,000 gates.
These requirements include high performance, on-chip
RAM, core solutions and prices that, in high volume,
approach and in many cases are equivalent to mask pro-
grammed ASIC devices.
The Spartan series is the result of more than 14 years of
FPGA design experience and feedback from thousands of
customers. By streamlining the Spartan series feature set,
leveraging advanced process technologies and focusing on
total cost management, the Spartan series delivers the key
features required by ASIC and other high-volume logic
users while avoiding the initial cost, long development
cycles and inherent risk of conventional ASICs. The Spar-
tan and Spartan-XL families in the Spartan series have ten
members, as shown in Table 1.
System level features
- Available in both 5V and 3.3V versions
- On-chip SelectRAMmemory
- Fully PCI compliant
- Full readback capability for program verification
and internal node observability
- Dedicated high-speed carry logic
- Internal 3-state bus capability
- Eight global low-skew clock or signal networks
- IEEE 1149.1-compatible Boundary Scan logic
- Low cost plastic packages available in all densities
- Footprint compatibility in common packages
Fully supported by powerful Xilinx development system
- Foundation Series: Integrated, shrink-wrap
software
- Alliance Series: Dozens of PC and workstation
third party development systems supported
- Fully automatic mapping, placement and routing
Spartan and Spartan-XL Features
Note: The Spartan series devices described in this data
sheet include the 5V Spartan family and the 3.3V
Spartan-XL family. See the separate data sheet for the 2.5V
Spartan-II family.
First ASIC replacement FPGA for high-volume
production with on-chip RAM
Density up to 1862 logic cells or 40,000 system gates
Streamlined feature set based on XC4000 architecture
System performance beyond 80 MHz
Broad set of AllianceCOREand LogiCORE
predefined solutions available
Unlimited reprogrammability
Low cost
Additional Spartan-XL Features
3.3V supply for low power with 5V tolerant I/Os
Power down input
Higher performance
Faster carry logic
More flexible high-speed clock network
Latch capability in Configurable Logic Blocks
Input fast capture latch
Optional mux or 2-input function generator on outputs
12 mA or 24 mA output drive
5V and 3.3V PCI compliant
Enhanced Boundary Scan
Express Mode configuration
Chip scale packaging
Table 1: Spartan and Spartan-XL Field Programmable Gate Arrays
Device
Max
Logic System
Typical
Gate Range
Cells Gates (Logic and RAM)(1)
CLB
Matrix
Max.
Total
Total No. of Avail. Distributed
CLBs Flip-flops User I/O RAM Bits
XCS05 and XCS05XL 238 5,000
2,000-5,000
10 x 10 100
360
77
3,200
XCS10 and XCS10XL 466 10,000
3,000-10,000
14 x 14 196
616
112
6,272
XCS20 and XCS20XL 950 20,000
7,000-20,000
20 x 20 400
1,120
160
12,800
XCS30 and XCS30XL 1368 30,000
10,000-30,000 24 x 24 576
1,536
192
18,432
XCS40 and XCS40XL 1862 40,000
13,000-40,000 28 x 28 784
2,016
224
25,088
Notes:
1. Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS060 (v1.6) September 19, 2001
Product Specification
www.xilinx.com
1-800-255-7778
1




XCS05XL pdf, 반도체, 판매, 대치품
Spartan and Spartan-XL Families Field Programmable Gate Arrays
R
G-LUT
G4 G4
Logic
G3 G3 Function
of G
G2 G2 G1-G4
G1 G1
SR
H1
DIN
B
H-LUT
G Logic
Function
H1 of H
F-G-H1
F
SR
DQ
CK
EC
YQ
Y
F4 F4
Logic
F3 F3 Function
of G
F2 F2 F1-F4
F1 F1
F-LUT
K
A
Multiplexer Controlled
by Configuration Program
SR
DQ
CK
EC
XQ
X
EC
DS060_02_0506 01
Figure 2: Spartan/XL Simplified CLB Logic Diagram (some features not shown)
A CLB can implement any of the following functions:
Any function of up to four variables, plus any second
function of up to four unrelated variables, plus any third
function of up to three unrelated variables
Note: When three separate functions are generated, one of
the function outputs must be captured in a flip-flop internal to
the CLB. Only two unregistered function generator outputs
are available from the CLB.
Any single function of five variables
Any function of four variables together with some
functions of six variables
Some functions of up to nine variables.
Implementing wide functions in a single block reduces both
the number of blocks required and the delay in the signal
path, achieving both increased capacity and speed.
The versatility of the CLB function generators significantly
improves system speed. In addition, the design-software
tools can deal with each function generator independently.
This flexibility improves cell usage.
Flip-Flops
Each CLB contains two flip-flops that can be used to regis-
ter (store) the function generator outputs. The flip-flops and
function generators can also be used independently (see
Figure 2). The CLB input DIN can be used as a direct input
to either of the two flip-flops. H1 can also drive either
flip-flop via the H-LUT with a slight additional delay.
The two flip-flops have common clock (CK), clock enable
(EC) and set/reset (SR) inputs. Internally both flip-flops are
also controlled by a global initialization signal (GSR) which
is described in detail in Global Signals: GSR and GTS,
page 20.
Latches (Spartan-XL only)
The Spartan-XL CLB storage elements can also be config-
ured as latches. The two latches have common clock (K)
and clock enable (EC) inputs. Functionality of the storage
element is described in Table 2.
4
www.xilinx.com
DS060 (v1.6) September 19, 2001
1-800-255-7778
Product Specification

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XCS05XL 전자부품, 판매, 대치품
R Spartan and Spartan-XL Families Field Programmable Gate Arrays
The register choice is made by placing the appropriate
library symbol. For example, IFD is the basic input flip-flop
(rising edge triggered), and ILD is the basic input latch
(transparent-High). Variations with inverted clocks are also
available. The clock signal inverter is also shown in Figure 5
on the CK line.
The Spartan IOB data input path has a one-tap delay ele-
ment: either the delay is inserted (default), or it is not. The
Spartan-XL IOB data input path has a two-tap delay ele-
ment, with choices of a full delay, a partial delay, or no delay.
The added delay guarantees a zero hold time with respect
to clocks routed through the global clock buffers. (See Glo-
bal Nets and Buffers, page 12 for a description of the glo-
bal clock buffers in the Spartan/XL families.) For a shorter
input register setup time, with positive hold-time, attach a
NODELAY attribute or property to the flip-flop.The output of
the input register goes to the routing channels (via I1 and I2
in Figure 6). The I1 and I2 signals that exit the IOB can each
carry either the direct or registered input signal.
The 5V Spartan input buffers can be globally configured for
either TTL (1.2V) or CMOS (VCC/2) thresholds, using an
option in the bitstream generation software. The Spartan
output levels are also configurable; the two global adjust-
ments of input threshold and output level are independent.
The inputs of Spartan devices can be driven by the outputs
of any 3.3V device, if the Spartan inputs are in TTL mode.
Input and output thresholds are TTL on all configuration
pins until the configuration has been loaded into the device
and specifies how they are to be used. Spartan-XL inputs
are TTL compatible and 3.3V CMOS compatible.
Supported sources for Spartan/XL device inputs are shown
in Table 4.
Spartan-XL I/Os are fully 5V tolerant even though the VCC is
3.3V. This allows 5V signals to directly connect to the Spar-
tan-XL inputs without damage, as shown in Table 4. In addi-
tion, the 3.3V VCC can be applied before or after 5V signals
are applied to the I/Os. This makes the Spartan-XL devices
immune to power supply sequencing problems.
GTS
T
O DQ
OUTPUT DRIVER
CK Programmable Slew Rate
OK Programmable TTL/CMOS Drive
EC (Spartan only)
Package
I1 Pad
INPUT BUFFER
I2 Delay
DQ
Programmable
IK CK
Pull-Up/
Pull-Down
EC
EC
Multiplexer Controlled
Network
by Configuration Program
Figure 6: Simplified Spartan/XL IOB Block Diagram
DS060_06_041901
DS060 (v1.6) September 19, 2001
Product Specification
www.xilinx.com
1-800-255-7778
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XCS05XL

Spartan and Spartan-XL Families Field Programmable Gate Arrays

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