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부품번호 | X24F064SI-5 기능 |
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기능 | SerialFlash TM Memory with Block Lock TM Protection | ||
제조업체 | Xicor | ||
로고 | |||
APPLICATION NOTE
A V A I LABLE
AN76 • AN78 • AN81 • AN87
64K/32K/16K
X24F064/032/016
8K/4K/2K x 8 Bit
SerialFlashTM Memory with Block LockTM Protection
FEATURES
• 1.8V to 3.6V or 5V “Univolt” Read and
Program Power Supply Versions
• Low Power CMOS
—Active Read Current Less Than 1mA
—Active Program Current Less Than 3mA
—Standby Current Less Than 1µA
• Internally Organized 8K/4K/2K x 8
• New Programmable Block Lock Protection
—Software Write Protection
—Programmable hardware Write Protect
• Block Lock (0, 1/4, 1/2, or all of the Flash
Memory array)
• 2 Wire Serial Interface
• Bidirectional Data Transfer Protocol
• 32 Byte Sector Programming
• Self Timed Program Cycle
—Typical Programming Time of 5ms
Per Sector
• High Reliability
—Endurance: 100,000 cycles per byte
—Data Retention: 100 Years
• Available Packages
—8-Lead PDIP
—8-Lead SOIC (JEDEC)
—14-Lead TSSOP (X24F032/016)
—20-Lead TSSOP (X24F064)
DESCRIPTION
The X24F064/032/016 is a CMOS SerialFlash
Memory Family, internally organized 8K/4K/2K x 8.
The family features a serial interface and software
protocol allowing operation on a simple two wire bus.
Device select inputs (S0, S1, S2) allow up to eight
devices to share a common two wire bus.
A Program Protect Register accessed at the highest
address location, provides three new programming
protection features: Software Programming Protection,
Block Lock Protection, and Hardware Programming
Protection. The Software Programming Protection
feature prevents any nonvolatile writes to the device
until the WEL bit in the program protect register is set.
The Block LockTM Protection feature allows the user to
individually protect four blocks of the array by program-
ming two bits in the programming protect register. The
Programmable Hardware Program Protect feature
allows the user to install each device with PP tied to
VCC, program the entire memory array in place, and
then enable the hardware programming protection by
programming a PPEN bit in the program protect
register. After this, selected blocks of the array,
including the program protect register itself, are
permanently protected from being programmed.
FUNCTIONAL DIAGRAM
SDA
SCL
DATA REGISTER
SECTOR DECODE LOGIC
32 8
S0/S0
S1/S1
S2/S2
COMMAND
DECODE
AND CONTROL
LOGIC
X
DECODE
LOGIC
PROGRAM
PROTECT
REGISTER
SECTORED
MEMORY
ARRAY
PP
PROGRAMMING
CONTROL LOGIC
SerialFlash™ Memory and Block Lock™
Protection are trademarks of Xicor, Inc.
©Xicor, 1995, 1996 Patents Pending
6686-3.8 8/29/96 T3/C0/D0 SH
1
HIGH VOLTAGE
CONTROL
6686 ILL F01.5
Characteristics subject to change without notice
X24F064/032/016
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the device into the standby power mode after a
read sequence. A stop condition can only be issued
after the transmitting device has released the bus.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 3.
Figure 3. Acknowledge Response From Receiver
The X24F064/032/016 will respond with an acknowl-
edge after recognition of a start condition and its slave
address. If both the device and a write operation have
been selected, the X24F064/032/016 will respond with
an acknowledge after the receipt of each subsequent
eight-bit word.
In the read mode the X24F064/032/016 will transmit
eight bits of data, release the SDA line and monitor
the line for an acknowledge. If an acknowledge is
detected and no stop condition is generated by the
master, the X24F064/032/016 will continue to
transmit data. If an acknowledge is not detected, the
device will terminate further data transmissions. The
master must then issue a stop condition to return the
X24F064/032/016 to the standby power mode and
place the device into a known state.
SCL FROM
MASTER
DATA OUTPUT
FROM
TRANSMITTER
1
89
DATA
OUTPUT
FROM
RECEIVER
START
ACKNOWLEDGE
6686 ILL F06
4
4페이지 X24F064/032/016
Current Address Read
Internally, the X24F064/032/016 contains an ad-
dress counter that maintains the address of the last
byte read, incremented by one byte. Therefore, if the
last read was from address n, the next read opera-
tion accesses data from address n + 1. Upon receipt
of the slave address with the R/W set HIGH, the
X24F064/032/016 issues an acknowledge and trans-
mits the eight-bit word. The read operation is termi-
nated by the master; by not responding with an
acknowledge and by issuing a stop condition. Refer
to Figure 6 for the sequence of address, acknowl-
edge and data transfer.
Random Read
Random read operations allow the master to access
any memory location in a random manner. Prior to is-
suing the slave address with the R/W bit set HIGH, the
master must first perform a “dummy” write operation.
The master issues the start condition, and the slave ad-
dress with the R/W bit set LOW, followed by the byte
address it is to read. After the byte address acknowl-
edge, the master immediately reissues the start condi-
tion and the slave address with the R/W bit set HIGH.
This will be followed by an acknowledge from the
X24F064/032/016 and then by the eight-bit byte. The
read operation is terminated by the master; by not re-
sponding with an acknowledge and by issuing a stop
condition. Refer to Figure 7 for the address, acknowl-
edge and data transfer sequence.
Figure 6. Current Address Read
S
BUS ACTIVITY:
MASTER
T
A
R
SLAVE
ADDRESS
T
SDA LINE
S
BUS ACTIVITY:
X24F016/032/064
A
C
K
S
T
O
P
P
DATA
6686 ILL F11.1
Figure 7. Random Read
BUS ACTIVITY:
MASTER
S
T
A
R
SLAVE
ADDRESS
T
SDA LINE
S
BUS ACTIVITY:
X24F016/032/064
BYTE
ADDRESS n
S
T
A
R
SLAVE
ADDRESS
T
S
AA
CC
KK
A
C
K
S
T
O
P
P
DATA n
6686 ILL F12.3
7
7페이지 | |||
구 성 | 총 18 페이지수 | ||
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부품번호 | 상세설명 및 기능 | 제조사 |
X24F064SI-5 | SerialFlash TM Memory with Block Lock TM Protection | Xicor |
X24F064SI-5 | SerialFlash TM Memory with Block Lock TM Protection | Xicor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |