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X24F128P-5 데이터시트 PDF




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부품번호 X24F128P-5 기능
기능 2-Wire SerialFlash with Block Lock TM Protection
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X24F128P-5 데이터시트, 핀배열, 회로
APPLICATION NOTE
A V A I LABLE
AN84
128K
X24F128
16K x 8 Bit
2-Wire SerialFlash with Block LockTM Protection
FEATURES
Save Critical Data With Programmable
Block Lock Protection
—Block Lock (0, 1/4, 1/2, or all of E2PROM Array)
—Software Program Protection
—Programmable Hardware Program Protect
In Circuit Programmable ROM Mode
Longer Battery Life With Lower Power
—Active Read Current Less Than 1mA
—Active Program Current Less Than 3mA
—Standby Current Less Than 1µA
1.8V to 3.6V or 5V “Univolt” Read and
Program Power Supply Versions
32 Word Sector Program Mode
—Minimizes Total Program Time Per Word
100KHz 2-Wire Serial Interface
Internally Organized 16K x 8
Bidirectional Data Transfer Protocol
Self-Timed Program Cycle
—Typical Program Cycle Time of 5ms
High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
8-Lead DIP
16-Lead SOIC
DESCRIPTION
The X24F128 is a CMOS SerialFlash Memory, inter-
nally organized 16K x 8. The device features a serial
interface and software protocol allowing operation on a
simple two wire bus.
Three device select inputs (S0–S2) allow up to eight
devices to share a common two wire bus.
A Program Protect Register at the address location
FFFFh provides three program protection features:
Software Program Protect, Block Lock Protect, and
Hardware Program Protect. The Software Program
Protect feature prevents any nonvolatile writes to the
device until the PEL bit in the Program Protect
Register is set. The Block Lock Protection feature
allows the user to individually block protect four blocks
of the array by programming two bits in the Program
Protect Register. The Programmable Hardware
Program Protect feature allows the user to install the
device with PP tied to VCC, program the entire memory
array in circuit, and then enable the hardware program
protection by programming a PPEN bit in the Program
Protect Register. After this, selected blocks of the
array, including the Program Protect Register itself, are
permanently protected from being erased.
FUNCTIONAL DIAGRAM
SERIALFLASH DATA
AND ADDRESS (SDA)
SCL
COMMAND
DECODE
AND
CONTROL
LOGIC
SECTOR
DECODE
LOGIC
BLOCK LOCK AND
PROGRAM PROTECT
CONTROL LOGIC
S2
DEVICE
S1 SELECT
LOGIC
S0
PROGRAM
PROTECT
REGISTER
DATA REGISTER
Y DECODE LOGIC
SERIALFLASH
ARRAY
16K x 8
4K x 8
4K x 8
8K x 8
PP
©Xicor, 1995, 1996 Patents Pending
7012-0.8 11/25/96 T1/C0/D0 SH
PROGRAM VOLTAGE
CONTROL
7012 ILL F01.4
Characteristics subject to change without notice
1




X24F128P-5 pdf, 반도체, 판매, 대치품
X24F128
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the device into the standby power mode after a
read sequence. A stop condition can only be issued
after the transmitting device has released the bus.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 3.
The device will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a program operation have been
selected, the device will respond with an acknowledge
after the receipt of each subsequent byte.
In the read mode the device will transmit eight bits of
data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. If an acknowledge is not
detected, the device will terminate further data trans-
missions. The master must then issue a stop condition
to return the device to the standby power mode and
place the device into a known state.
Figure 3. Acknowledge Response From Receiver
SCL FROM
MASTER
DATA OUTPUT
FROM
TRANSMITTER
1
89
DATA
OUTPUT
FROM
RECEIVER
START
ACKNOWLEDGE
7012 ILL F05
4

4페이지










X24F128P-5 전자부품, 판매, 대치품
X24F128
Acknowledge Polling
The maximum program cycle time can be significantly
reduced using Acknowledge Polling. To initiate
Acknowledge Polling, the master issues a start condi-
tion followed by the Slave Address Byte for a program
or read operation. If the device is still busy with the
nonvolatile write cycle, then no ACK will be returned. If
the device has completed the nonvolatile write opera-
tion, an ACK will be returned and the host can then
proceed with the read or program operation. Refer to
figure 6.
Figure 6. Acknowledge Polling Sequence
BYTE LOAD COMPLETED
BY ISSUING STOP.
ENTER ACK POLLING
ISSUE
START
ISSUE SLAVE
ADDRESS BYTE
(READ OR PROGRAM)
ISSUE STOP
ACK
RETURNED?
YES
NO
NONVOLATILE
WRITE
CYCLE COMPLETE.
CONTINUE
SEQUENCE?
YES
CONTINUE NORMAL
READ OR PROGRAM
COMMAND SEQUENCE
NO
ISSUE STOP
READ OPERATIONS
Read operations are initiated in the same manner as
program operations with the exception that the R/W bit
of the Slave Address Byte is set to one. There are
three basic read operations: Current Address Reads,
Random Reads, and Sequential Reads.
Current Address Read
Internally, the device contains an address counter that
maintains the address of the last byte read or
programmed, incremented by one. After a read opera-
tion from the last address in the array, the counter will
“roll over” to the first address in the array. After a
program operation to the last address in a given sector,
the counter will “roll over” to the first address of the
same sector.
Upon receipt of the Slave Address Byte with the R/W
bit set to one, the device issues an acknowledge and
then transmits the byte at the current address. The
master terminates the read operation when it does not
respond with an acknowledge during the ninth clock
and then issues a stop condition. Refer to figure 7 for
the address, acknowledge, and data transfer
sequence.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
Figure 7. Current Address Read Sequence
SIGNALS
FROM THE
MASTER
SDA BUS
SIGNALS
FROM THE
SLAVE
S
T
A
R
SLAVE
ADDRESS
T
S1010
1
A
C
K
S
T
O
P
P
DATA
7012 ILL F10
PROCEED
7012 ILL F09
7

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부품번호상세설명 및 기능제조사
X24F128P-5

2-Wire SerialFlash with Block Lock TM Protection

Xicor
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