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X25040SM 데이터시트 PDF




Xicor에서 제조한 전자 부품 X25040SM은 전자 산업 및 응용 분야에서
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부품번호 X25040SM 기능
기능 SPI Serial E2PROM with Block LockTM Protection
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X25040SM 데이터시트, 핀배열, 회로
APPLICATION NOTES
AVA I L A B L E
X25040AN9 • AN18 • AN31 • AN37 • AN40
4K
X25040
512 x 8 Bit
SPI Serial E2PROM with Block LockTM Protection
FEATURES
1MHz Clock Rate
SPI Modes (0,0 & 1,1)
512 X 8 Bits
—4 Byte Page Mode
Low Power CMOS
—150µA Standby Current
—3mA Active Current
2.7V To 5.5V Power Supply
Block Lock Protection
—Protect 1/4, 1/2 or all of E2PROM Array
Built-in Inadvertent Write Protection
—Power-Up/Power-Down protection circuitry
—Write Latch
—Write Protect Pin
Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
High Reliability
—Endurance: 100,000 cycles per byte
—Data Retention: 100 Years
—ESD protection: 2000V on all pins
8-Lead PDlP Package
8-Lead SOIC Package
DESCRIPTION
The X25040 is a CMOS 4096-bit serial E2PROM, inter-
nally organized as 512 x 8. The X25040 features a Serial
Peripheral Interface (SPI) and software protocol allow-
ing operation on a simple three-wire bus. The bus
signals are a clock input (SCK) plus separate data in (SI)
and data out (SO) lines. Access to the device is con-
trolled through a chip select (CS) input, allowing any
number of devices to share the same bus.
The X25040 also features two additional inputs that
provide the end user with added flexibility. By asserting
the HOLD input, the X25040 will ignore transitions on its
inputs, thus allowing the host to service higher priority
interrupts. The WP input can be used as a hardwire input
to the X25040 disabling all write attempts, thus providing
a mechanism for limiting end user capability of altering
the memory.
The X25040 utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000 cycles
per byte and a minimum data retention of 100 years.
FUNCTIONAL DIAGRAM
STATUS
REGISTER
SO
SI
SCK
CS
HOLD
COMMAND
DECODE
AND
CONTROL
LOGIC
WRITE
PROTECT
LOGIC
X DECODE
LOGIC
32
32
64
512 BYTE
ARRAY
32 X 32
32 X 32
64 X 32
WRITE
CONTROL
AND
WP TIMING
LOGIC
Direct Write™ and Block Lock™ Protection is a trademark of Xicor, Inc.
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
6451-3.6 6/10/96 T5/C1/D0 NS
1
48
Y DECODE
DATA REGISTER
6451 FHD F01
Characteristics subject to change without notice




X25040SM pdf, 반도체, 판매, 대치품
X25040
Clock and Data Timing
Data input on the SI line is latched on the rising edge of
SCK. Data is output on the SO line by the falling edge of
SCK.
Read Sequence
When reading from the E2PROM memory array, CS is
first pulled LOW to select the device. The 8-bit READ
instruction is transmitted to the X25040, followed by the
8-bit address. Bit 3 of the Read Data instruction con-
tains address A8. This bit is used to select the upper or
lower half of the address. After the READ opcode and
address are sent, the data stored in the memory at the
selected address is shifted out on the SO line. The data
stored in memory at the next address can be read
sequentially by continuing to provide clock pulses. The
address is automatically incremented to the next higher
address after each byte of data is shifted out. When the
highest address is reached ($1FF) the address counter
rolls over to address $000 allowing the read cycle to be
continued indefinitely. The read operation is termi-
nated by taking CS HIGH. Refer to the read E2PROM
array operation sequence illustrated in Figure 1.
To read the status register, the CS line is first pulled
LOW to select the device followed by the 8-bit RDSR
instruction. After the read status register opcode is
sent, the contents of the status register are shifted out
on the SO line. Figure 2 illustrates the read status
register sequence.
Write Sequence
Prior to any attempt to write data into the X25040, the
“write enable” latch must first be set by issuing the
WREN instruction (See Figure 3). CS is first taken LOW,
then the WREN instruction is clocked into the X25040.
After all eight bits of the instruction are transmitted, CS
must then be taken HIGH. If the user continues the write
operation without taking CS HIGH after issuing the
WREN instruction, the write operation will be ignored.
To write data to the E2PROM memory array, the user
issues the WRITE instruction, followed by the address
and then the data to be written. This is minimally a
twenty-four clock operation. CS must go LOW and
remain LOW for the duration of the operation. The host
may continue to write up to 4 bytes of data to the X25040.
The only restriction is the 4 bytes must reside on the
same page. If the address counter reaches the end of
the page and the clock continues, the counter will “roll
over” to the first address of the page and overwrite any
data that may have been written.
For the write operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of
data byte N is clocked in. If it is brought HIGH at any other
time the write operation will not be completed. Refer to
Figures 4 and 5 below for a detailed illustration of the
write sequences and time frames in which CS going
HIGH are valid.
To write to the status register, the WRSR instruction is
followed by the data to be written. Data bits 0, 1, 4, 5, 6
and 7 must be “0”. Figure 6 illustrates this sequence.
While the write is in progress following a status register
or E2PROM write sequence, the status register may be
read to check the WIP bit. During this time the WIP bit will
be HIGH.
Hold Operation
The HOLD input should be HIGH (at VIH) under normal
operation. If a data transfer is to be interrupted HOLD
can be pulled LOW to suspend the transfer until it can be
resumed. The only restriction is the SCK input must be
LOW when HOLD is first pulled LOW and SCK must also
be LOW when HOLD is released.
The HOLD input may be tied HIGH either directly to VCC
or tied to VCC through a resistor.
4

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X25040SM 전자부품, 판매, 대치품
X25040
Figure 5. Page Write Operation Sequence
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
INSTRUCTION
BYTE ADDRESS
DATA BYTE 1
SI 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
9TH BIT OF ADDRESS
CS
SCK
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
DATA BYTE 2
DATA BYTE 3
DATA BYTE 4
SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
6451 FHD F07
Figure 6. Write Status Register Operation Sequence
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INSTRUCTION
DATA BYTE
SI 7 6 5 4 3 2 1 0
HIGH IMPEDANCE
SO
6451 ILL F08
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