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X25097S-2.7 데이터시트 PDF




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부품번호 X25097S-2.7 기능
기능 5MHz Low Power SPI Serial E 2 PROM with IDLock TM Memory
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X25097S-2.7 데이터시트, 핀배열, 회로
8K
X25097
1024 x 8 Bit
5MHz Low Power SPI Serial E2PROM with IDLockTM Memory
FEATURES
• 5MHz Clock Rate
• IDLock™ Memory
—IDLock First or Last Page, any 1/4 or Lower 1/2
of E2PROM Array
• Low Power CMOS
—<1µA Standby Current
—<3mA Active Current during Write
—<400µA Active Current during Read
• 1.8V to 3.6V, 2.7V-5.5V or 4.5V to 5.5V Operation
• Built-in Inadvertent Write Protection
—Power-Up/Power-Down Protection Circuitry
—Write Enable Latch
—Write Protect Pin
• SPI Modes (0,0 & 1,1)
• 1024 x 8 Bits
—16 Byte Page Mode
• Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
• High Reliability
—Endurance: 100,000 Cycles/Byte
—Data Retention: 100 Years
—ESD: 2000V on all pins
• 8-Lead TSSOP Package
• 8-Lead SOIC Package
• 8-Lead PDIP Package
DESCRIPTION
The X25097 is a CMOS 8K-bit serial E2PROM, internally
organized as 1024 x 8. The X25097 features a Serial
Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus. The bus
signals are a clock input (SCK) plus separate data in (SI)
and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing any
number of devices to share the same bus.
IDLock is a programmble locking mechanism which
allows the user to lock system ID and parametric data in
different portions of the E2PROM memory space,
ranging from as little as one page to as much as 1/2 of
the total array. The X25097 also features a WP pin that
can be used for hardwire protection of the part, disabling
all write attempts, as well as a Write Enable Latch that
must be set before a write operation can be initiated.
The X25097 utilizes Xicor’s proprietary Direct WriteTM
cell, providing a minimum endurance of 100,000 cycles
per byte and a minimum data retention of 100 years.
FUNCTIONAL DIAGRAM
SI
SO
SCK
COMMAND
DECODE
AND
CONTROL
LOGIC
CS
X
DECODE
LOGIC
DATA REGISTER
Y DECODE LOGIC
16 8
64
8K E2PROM
ARRAY
(1024 x 8)
WP WRITE CONTROL LOGIC
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
7034-1.1 5/8/97 T1/C0/D0 SH
1
HIGH VOLTAGE
CONTROL
7038 FRM F01
Characteristics subject to change without notice




X25097S-2.7 pdf, 반도체, 판매, 대치품
X25097
IDLock Operation
Prior to any attempt to perform an IDLock Operation, the
WREN instruction must first be issued. This instruction
sets the “Write Enable” latch and allows the part to
respond to an IDLock sequence (Figure 7). The IDLock
instruction follows and consists of one command byte fol-
lowed by one IDLock byte (See Figure 1). This byte con-
tains the IDLock bits IDL2-IDL0. The rest of the bits [7:3]
are unused and must be written as zeroes. Bringing CS
HIGH after the two byte IDLock instruction initiates a
nonvolatile write to the Status Register. Writing more
than one byte to the Status Register will overwrite the
previously written IDLock byte. See Table 1.
Operational Notes
The X25097 powers up in the following state:
• The device is in the low power, standby state.
• A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
• SO pin is at high impedance.
• The “Write Enable” latch is reset.
Data Protection
The following circuitry has been included to prevent inad-
vertant writes:
• The “Write Enable” latch is reset upon power-up.
• A WREN instruction must be issued to set the “Write
Enable” latch.
• CS must come HIGH at the proper clock count in order
to start a write cycle.
Table 1. Instruction Set and Block Lock Protection Byte Definition
Instruction Format*
Instruction Name and Operation
0000 0110
WREN: Set the Write Enable Latch (Write Enable Operation)
0000 0100
WRDI: Reset the Write Enable Latch (Write Disable Operation)
0000 0001
IDLock Instruction—followed by:
IDLock Byte: (See Figure 1)
0000 0000 --->NO IDLock: 00h-00h - - - - - - - - - - - >None of the Array
0000 0001 --->IDLock Q1: 0000h-00FFh - - - - - - - >Lower Quadrant (Q1)
0000 0010 --->IDLock Q2: 0100h-01FFh - - - - - - - >Q2
0000 0011 --->IDLock Q3: 0200h-02FFh - - - - - - - >Q3
0000 0100 --->IDLock Q4: 0300h-03FFh - - - - - - - >Upper Quadrant (Q4)
0000 0101 --->IDLock H1: 0000h-01FFh - - - - - - - >Lower Half of the Array (H1)
0000 0110 --->IDLock P0: 0000h-000Fh - - - - - - - >Lower Page (P0)
0000 0111 --->IDLock Pn: 03F0h-03FFh - - - - - - - >Upper Page (Pn)
0000 0101
READ STATUS: Reads IDLock & write in progress status on SO Pin
0000 0010
WRITE: Write operation followed by address and data
0000 0011
READ: Read operation followed by address
*Instructions are shown with MSB in leftmost position. Instructions are transferred MSB first.
7038 FRM T03
4

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X25097S-2.7 전자부품, 판매, 대치품
X25097
Figure 6. Page Write Operation Sequence
CS
SCK
SI
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23 24 25 26 27 28 29 30 31
PROGRAM
INSTRUCTION
BYTE ADDRESS
(2 BYTE)
DATA BYTE 1
15 14 13
321076543210
CS
SCK
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
DATA BYTE 2
DATA BYTE 3
SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Figure 7. IDLock Operation Sequence
CS
DATA BYTE 16
6543210
7038 FRM F07.3
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
IDLock
INSTRUCTION
HIGH IMPEDANCE
IDLock
BYTE
I II
0
0
0
0
0
D
L
DD
LL
2 10
7038 FRM F08.2
7

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부품번호상세설명 및 기능제조사
X25097S-2.7

5MHz Low Power SPI Serial E 2 PROM with IDLock TM Memory

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