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부품번호 | X25128SM 기능 |
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기능 | SPI Serial E 2 PROM with Block Lock TM Protection | ||
제조업체 | Xicor | ||
로고 | |||
전체 15 페이지수
APPLICATION NOTE
A VA I L A B L E
AN61
128K
X25128
SPI Serial E2PROM with Block LockTM Protection
16K x 8 Bit
FEATURES
• 2MHz Clock Rate
• SPI Modes (0,0 & 1,1)
• 16K X 8 Bits
—32 Byte Page Mode
• Low Power CMOS
—<1µA Standby Current
—<5mA Active Current
• 2.7V To 5.5V Power Supply
• Block Lock Protection
—Protect 1/4, 1/2 or all of E2PROM Array
• Built-in Inadvertent Write Protection
—Power-Up/Power-Down protection circuitry
—Write Enable Latch
—Write Protect Pin
• Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
• High Reliability
—Endurance: 100,000 cycles
—Data Retention: 100 Years
—ESD protection: 2000V on all pins
• 14-Lead SOIC Package
• 16-Lead SOIC Package
• 8-Lead PDIP Package
FUNCTIONAL DIAGRAM
STATUS
REGISTER
WRITE
PROTECT
LOGIC
SO
SI
SCK
CS
HOLD
COMMAND
DECODE
AND
CONTROL
LOGIC
DESCRIPTION
The X25128 is a CMOS 131,072-bit serial E2PROM,
internally organized as 16K x 8. The X25128 features
a Serial Peripheral Interface (SPI) and software
protocol allowing operation on a simple three-wire bus.
The bus signals are a clock input (SCK) plus separate
data in (SI) and data out (SO) lines. Access to the
device is controlled through a chip select (CS) input,
allowing any number of devices to share the same
bus.
The X25128 also features two additional inputs that
provide the end user with added flexibility. By
asserting the HOLD input, the X25128 will ignore tran-
sitions on its inputs, thus allowing the host to service
higher priority interrupts. The WP input can be used as
a hardwire input to the X25128 disabling all write
attempts to the status register, thus providing a mech-
anism for limiting end user capability of altering 0, 1/4,
1/2 or all of the memory.
The X25128 utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
X DECODE
LOGIC
128
128
256
16K BYTE
ARRAY
16 X 256
16 X 256
32 X 256
WRITE
CONTROL
AND
WP
TIMING
LOGIC
32 8
Y DECODE
DATA REGISTER
3091 FM F01
©Xicor Inc. 1994, 1995, 1996 Patents Pending
3091-2.9 5/14/97 T2/C0/D2 SH
Characteristics subject to change without notice
1
X25128
Write-Protect Enable
The Write-Protect-Enable (WPEN) is available for the
X25128 as a nonvolatile enable bit for the WP pin.
Protected Unprotected Status
WPEN WP WEL Blocks Blocks Register
0 X 0 Protected Protected Protected
0 X 1 Protected Writable Writable
1 Low 0 Protected Protected Protected
1 Low 1 Protected Writable Protected
X High 0 Protected Protected Protected
X High 1 Protected Writable Writable
3091 PGM T05.1
The Write Protect (WP) pin and the nonvolatile Write
Protect Enable (WPEN) bit in the Status Register
control the programmable hardware write protect
feature. Hardware write protection is enabled when
WP pin is low, and the WPEN bit is “1”. Hardware write
protection is disabled when either the WP pin is high
or the WPEN bit is “0”. When the chip is hardware
write protected, nonvolatile writes are disabled to the
Status Register, including the Block Protect bits and
the WPEN bit itself, as well as the block-protected
sections in the memory array. Only the sections of the
memory array that are not block-protected can be
written.
Note: Since the WPEN bit is write protected, it
cannot be changed back to a “0”, as long as
the WP pin is held low.
Clock and Data Timing
Data input on the SI line is latched on the rising edge
of SCK. Data is output on the SO line by the falling
edge of SCK.
Read Sequence
When reading from the E2PROM array, CS is first
pulled low to select the device. The 8-bit read instruc-
tion is transmitted to the X25128, followed by the
16-bit address of which the last 14 are used. After the
read opcode and address are sent, the data stored in
the memory at the selected address is shifted out on
the SO line. The data stored in memory at the next
address can be read sequentially by continuing to
provide clock pulses. The address is automatically
incremented to the next higher address after each byte
of data is shifted out. When the highest address is
reached ($3FFF) the address counter rolls over to
address $0000 allowing the read cycle to be continued
indefinitely. The read operation is terminated by taking
CS high. Refer to the read E2PROM array operation
sequence illustrated in Figure 1.
To read the status register the CS line is first pulled
low to select the device followed by the 8-bit instruc-
tion. After the RDSR opcode is sent, the contents of
the status register are shifted out on the SO line. The
read status register sequence is illustrated in Figure 2.
Write Sequence
Prior to any attempt to write data into the X25128, the
“write enable” latch must first be set by issuing the
WREN instruction (See Figure 3). CS is first taken low,
then the WREN instruction is clocked into the X25128.
After all eight bits of the instruction are transmitted, CS
must then be taken high. If the user continues the write
operation without taking CS high after issuing the
WREN instruction, the write operation will be ignored.
To write data to the E2PROM memory array, the user
issues the write instruction, followed by the address
and then the data to be written. This is minimally a
thirty-two clock operation. CS must go low and remain
low for the duration of the operation. The host may
continue to write up to 32 bytes of data to the X25128.
The only restriction is the 32 bytes must reside on the
same page. If the address counter reaches the end of
the page and the clock continues, the counter will “roll
over” to the first address of the page and overwrite any
data that may have been written.
For the write operation (byte or page write) to be
completed, CS can only be brought high after bit 0 of
data byte N is clocked in. If it is brought high at any
other time the write operation will not be completed.
Refer to Figures 4 and 5 below for a detailed illustra-
tion of the write sequences and time frames in which
CS going high are valid.
To write to the status register, the WRSR instruction is
followed by the data to be written. Data bits 0, 1, 4, 5
and 6 must be “0”. This sequence is shown in Figure 6.
While the write is in progress, following a status
register or E2PROM write sequence, the status
register may be read to check the WIP bit. During this
time the WIP bit will be high.
Hold Operation
The HOLD input should be high (at VIH) under normal
operation. If a data transfer is to be interrupted HOLD
can be pulled low to suspend the transfer until it can
be resumed. The only restriction is the SCK input must
4
4페이지 X25128
Figure 5. Page Write Operation Sequence
CS
SCK
SI
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23 24 25 26 27 28 29 30 31
INSTRUCTION
16 BIT ADDRESS
DATA BYTE 1
15 14 13
321076543210
CS
SCK
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
DATA BYTE 2
DATA BYTE 3
SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
DATA BYTE N
6543210
3091 FM F07
Figure 6. Write Status Register Operation Sequence
CS
SCK
SI
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INSTRUCTION
DATA BYTE
76543210
HIGH IMPEDANCE
SO
3091 FM F08
7
7페이지 | |||
구 성 | 총 15 페이지수 | ||
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구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
X25128S | SPI Serial E 2 PROM with Block Lock TM Protection | Xicor |
X25128S-2.7 | SPI Serial E 2 PROM with Block Lock TM Protection | Xicor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |