Datasheet.kr   

X25138V8-V 데이터시트 PDF




Xicor에서 제조한 전자 부품 X25138V8-V은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 X25138V8-V 자료 제공

부품번호 X25138V8-V 기능
기능 5MHz SPI Serial E2PROM with Block Lock PROTECTION
제조업체 Xicor
로고 Xicor 로고


X25138V8-V 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.



전체 18 페이지수

미리보기를 사용할 수 없습니다

X25138V8-V 데이터시트, 핀배열, 회로
128K
X25138
16K x 8 Bit
5MHz SPI Serial E2PROM with Block LockTM Protection
FEATURES
5MHz Clock Rate
Low Power CMOS
<1mA Standby Current
<5mA Active Current
2.5V To 5.5V Power Supply
SPI Modes (0,0 & 1,1)
16K X 8 Bits
32 Byte Page Mode
Block Lock™ Protection
Protect 1/4, 1/2 or all of E2PROM Array
Programmable Hardware Write Protection
In-Circuit Programmable ROM Mode
Built-in Inadvertent Write Protection
Power-Up/Down protection circuitry
Write Enable Latch
Write Protect Pin
Self-Timed Write Cycle
5ms Write Cycle Time (Typical)
High Reliability
Endurance: 100,000 cycles
Data Retention: 100 Years
ESD protection: 2000V on all pins
Packages
8-Lead XBGA
8, 14-Lead SOIC
8-Lead PDIP
8-Lead TSSOP
FUNCTIONAL DIAGRAM
STATUS
REGISTER
WRITE
PROTECT
LOGIC
SO
SI
SCK
CS
HOLD
COMMAND
DECODE
AND
CONTROL
LOGIC
DESCRIPTION
The X25138 is a CMOS 128K-bit serial E2PROM,
internally organized as 16K x 8. The X25138 features
a Serial Peripheral Interface (SPI) and software
protocol allowing operation on a simple three-wire bus.
The bus signals are a clock input (SCK) plus separate
data in (SI) and data out (SO) lines. Access to the
device is controlled through a chip select (CS) input,
allowing any number of devices to share the same
bus.
The X25138 also features two additional inputs that
provide the end user with added flexibility. By
asserting the HOLD input, the X25138 will ignore tran-
sitions on its inputs, thus allowing the host to service
higher priority interrupts. The WP input can be used as
a hardwire input to the X25138 disabling all write
attempts to the status register, thus providing a mech-
anism for limiting end user capability of altering 0, 1/4,
1/2 or all of the memory.
The X25138 utilizes Xicor’s proprietary Direct WriteTM
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
X DECODE
LOGIC
128
16K BYTE
ARRAY
128 X 256
128
128 X 256
256
256 X 256
WRITE
CONTROL
AND
WP
TIMING
LOGIC
Direct WriteÔ and Block LockÔ Protection is a trademark of Xicor, Inc.
ÓXicor, Inc. 1998 Patents Pending
7056–1.5 8/13/98 T2/C0/D1 EW
1
32 8
Y DECODE
DATA REGISTER
7037 FRM F01
Characteristics subject to change without notice




X25138V8-V pdf, 반도체, 판매, 대치품
X25138
The Write-Protect-Enable (WPEN) bit is available for
the X25138 as a nonvolatile enable bit for the WP pin.
Protected Unprotected Status
WPEN WP WEL Blocks
Blocks Register
0 X 0 Protected Protected Protected
0 X 1 Protected Writable Writable
1 LOW 0 Protected Protected Protected
1 LOW 1 Protected Writable Protected
X HIGH 0 Protected Protected Protected
X HIGH 1 Protected Writable Writable
7037 FRM T05
Programmable Hardware Write Protection
The Write Protect (WP) pin and the nonvolatile Write
Protect Enable (WPEN) bit in the Status Register
control the Programmable Hardware Write Protect
feature. Hardware Write Protection is enabled when
WP pin is LOW, and the WPEN bit is “1”. Hardware
Write Protection is disabled when either the WP pin is
HIGH or the WPEN bit is “0”. When the chip is hard-
ware write protected, nonvolatile writes are disabled to
the Status Register, including the Block Lock bits and
the WPEN bit itself, as well as the block-protected
sections in the memory array. Only the sections of the
memory array that are not block-protected can be
written.
In Circuit Programmable ROM Mode
Note that since the WPEN bit is write protected, it
cannot be changed back to a LOW state; so write
protection is enabled as long as the WP pin is held
LOW. Thus an In Circuit Programmable ROM function
can be emplemented by hardwiring the WP pin to Vss,
writing to and Block Locking the desired portion of the
array to be ROM, and then programming the WPEN bit
HIGH. The table above defines the program protect
status for each combination of WPEN and WP.
Clock and Data Timing
Data input on the SI line is latched on the rising edge
of SCK. Data is output on the SO line by the falling
edge of SCK.
Read Sequence
When reading from the E2PROM memory array, CS is
first pulled LOW to select the device. The 8-bit READ
instruction is transmitted to the X25138, followed by
the 16-bit address of which the last 14 are used. After
the READ opcode and address are sent, the data
stored in the memory at the selected address is
shifted out on the SO line. The data stored in memory
at the next address can be read sequentially by
continuing to provide clock pulses. The address is
automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address is reached ($3FFF) the address counter rolls
over to address $0000 allowing the read cycle to be
continued indefinitely. The read operation is termi-
nated by taking CS HIGH. Refer to the read E2PROM
array operation sequence illustrated in Figure 1.
To read the status register the CS line is first pulled
LOW to select the device followed by the 8-bit RDSR
instruction. After the RDSR opcode is sent, the contents
of the status register are shifted out on the SO line.
Figure 2 illustrates the read status register sequence.
Write Sequence
Prior to any attempt to write data into the X25138, the
“write enable” latch must first be set by issuing the
WREN instruction (See Figure 3). CS is first taken
LOW, then the WREN instruction is clocked into the
X25138. After all eight bits of the instruction are trans-
mitted, CS must then be taken HIGH. If the user
continues the write operation without taking CS HIGH
after issuing the WREN instruction, the write operation
will be ignored.
To write data to the E2PROM memory array, the user
issues the WRITE instruction, followed by the address
and then the data to be written. This is minimally a
thirty-two clock operation. CS must go LOW and remain
LOW for the duration of the operation. The host may
continue to write up to 32 bytes of data to the X25138.
The only restriction is the 32 bytes must reside on the
same page. If the address counter reaches the end of
the page and the clock continues, the counter will “roll
over” to the first address of the page and overwrite any
data that may have been written.
For the write operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of
data byte N is clocked in. If it is brought HIGH at any
other time the write operation will not be completed.
Refer to Figures 4 and 5 below for a detailed illustra-
tion of the write sequences and time frames in which
CS going HIGH are valid.
To write to the status register, the WRSR instruction is
followed by the data to be written. Data bits 0, 1, 4, 5
and 6 must be “0”. Figure 6 illustrates this sequence.
While the write is in progress following a status
register or E2PROM write sequence, the status
register may be read to check the WIP bit. During this
time the WIP bit will be HIGH.
4

4페이지










X25138V8-V 전자부품, 판매, 대치품
X25138
Figure 5. Page Write Operation Sequence
CS
SCK
SI
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23 24 25 26 27 28 29 30 31
INSTRUCTION
16 BIT ADDRESS
DATA BYTE 1
15 14 13
32107654 3210
CS
SCK
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
DATA BYTE 2
DATA BYTE 3
SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
DATA BYTE N
6543210
7037 FRM F07
Figure 6. Write Status Register Operation Sequence
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INSTRUCTION
DATA BYTE
SI 7 6 5 4 3 2 1 0
HIGH IMPEDANCE
SO
7037 FRM F08
7

7페이지


구       성 총 18 페이지수
다운로드[ X25138V8-V.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
X25138V8-V

5MHz SPI Serial E2PROM with Block Lock PROTECTION

Xicor
Xicor

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵