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X28C64DMB-25 데이터시트 PDF




Xicor에서 제조한 전자 부품 X28C64DMB-25은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 X28C64DMB-25 자료 제공

부품번호 X28C64DMB-25 기능
기능 5 Volt/ Byte Alterable E2PROM
제조업체 Xicor
로고 Xicor 로고


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X28C64DMB-25 데이터시트, 핀배열, 회로
X28C64
64K
X28C64
8K x 8 Bit
5 Volt, Byte Alterable E2PROM
FEATURES
150ns Access Time
Simple Byte and Page Write
—Single 5V Supply
—No External High Voltages or VPP Control
Circuits
—Self-Timed
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
Low Power CMOS
—60mA Active Current Max.
—200µA Standby Current Max.
Fast Write Cycle Times
—64 Byte Page Write Operation
—Byte or Page Write Cycle: 5ms Typical
—Complete Memory Rewrite: 0.625 sec. Typical
—Effective Byte Write Cycle Time: 78µs Typical
Software Data Protection
End of Write Detection
DATA Polling
—Toggle Bit
High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
JEDEC Approved Byte-Wide Pinout
PIN CONFIGURATION
DESCRIPTION
The X28C64 is an 8K x 8 E2PROM, fabricated with
Xicor’s proprietary, high performance, floating gate
CMOS technology. Like all Xicor programmable non-
volatile memories the X28C64 is a 5V only device. The
X28C64 features the JEDEC approved pinout for byte-
wide memories, compatible with industry standard RAMs.
The X28C64 supports a 64-byte page write operation,
effectively providing a 78µs/byte write cycle and en-
abling the entire memory to be typically written in 0.625
seconds. The X28C64 also features DATA and Toggle
Bit Polling, a system software support scheme used to
indicate the early completion of a write cycle. In addi-
tion, the X28C64 includes a user-optional software data
protection mode that further enhances Xicor’s hard-
ware write protect capability.
Xicor E2PROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data re-
tention is greater than 100 years.
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
PLASTIC DIP
CERDIP
FLAT PACK
SOIC
1 28
2 27
3 26
4 25
5 24
6 23
7 22
X28C64
8 21
9 20
10 19
11 18
12 17
13 16
14 15
VCC
WE
NC
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/04
I/O3
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
3853 FHD F02
LCC
PLCC
4 3 2 1 32 31 30
5 29
6 28
7 27
8 26
9
X28C64
25
10 24
11 23
12 22
13 21
14 15 16 17 18 19 20
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
3853 FHD F03
A2
A1
A0
I/O0
I/O1
I/O2
NC
VSS
NC
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TSOP
X28C64
32 A3
31 A4
30 A5
29 A6
28 A7
27 A12
26 NC
25 NC
24 VCC
23 NC
22 WE
21 NC
20 A8
19 A9
18 A11
17 OE
3853 ILL F23.1
© Xicor, Inc. 1991, 1995 Patents Pending
3853-2.7 4/2/96 T0/C3/D2 NS
1 Characteristics subject to change without notice




X28C64DMB-25 pdf, 반도체, 판매, 대치품
X28C64
DATA Polling I/O7
Figure 2. DATA Polling Bus Sequence
LAST
WE WRITE
CE
OE
VIH
I/O7
A0–A12
An
HIGH Z
VOL
An An
An
An
VOH
X28C64
READY
An An
3853 FHD F12
Figure 3. DATA Polling Software Flow
WRITE DATA
DATA Polling can effectively halve the time for writing to
the X28C64. The timing diagram in Figure 2 illustrates
the sequence of events on the bus. The software flow
diagram in Figure 3 illustrates one method of implement-
ing the routine.
WRITES
COMPLETE?
NO
YES
SAVE LAST DATA
AND ADDRESS
READ LAST
ADDRESS
IO7
COMPARE?
YES
NO
X28C64
READY
3853 FHD F13
4

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X28C64DMB-25 전자부품, 판매, 대치품
X28C64
Software Data Protection
Figure 6. Timing Sequence—Byte or Page Write
VCC
0V
DATA AA
ADDRESS 1555
CE
55
0AAA
WE
A0
1555
tWPH2
tBLC MAX
WRITES
OK
BYTE
OR
PAGE
tWC
(VCC)
WRITE
PROTECTED
3853 FHD F16
Figure 7. Write Sequence for Software Data
Protection
WRITE DATA AA
TO ADDRESS
1555
WRITE DATA 55
TO ADDRESS
0AAA
WRITE DATA A0
TO ADDRESS
1555
WRITE DATA XX
TO ANY
ADDRESS
BYTE/PAGE
LOAD ENABLED
Regardless of whether the device has previously been
protected or not, once the software data protection
algorithm is used and data has been written, the X28C64
will automatically disable further writes unless another
command is issued to cancel it. If no further commands
are issued the X28C64 will be write protected during
power-down and after any subsequent power-up.
Note: Once initiated, the sequence of write operations
should not be interrupted.
WRITE LAST
BYTE TO
LAST ADDRESS
AFTER tWC
RE-ENTERS DATA
PROTECTED STATE
3853 FHD F17
3853 FHD F17
7

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