|
|
|
부품번호 | X28HC64S-70 기능 |
|
|
기능 | 5 Volt/ Byte Alterable E2PROM | ||
제조업체 | Xicor | ||
로고 | |||
전체 24 페이지수
X28HC64
64K
X28HC64
8K x 8 Bit
5 Volt, Byte Alterable E2PROM
FEATURES
• 55ns Access Time
• Simple Byte and Page Write
—Single 5V Supply
—No External High Voltages or VPP Control
Circuits
—Self-Timed
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
• Low Power CMOS
—40 mA Active Current Max.
—200 µA Standby Current Max.
• Fast Write Cycle Times
—64 Byte Page Write Operation
—Byte or Page Write Cycle: 2ms Typical
—Complete Memory Rewrite: 0.25 sec. Typical
—Effective Byte Write Cycle Time: 32µs Typical
• Software Data Protection
• End of Write Detection
—DATA Polling
—Toggle Bit
• High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
• JEDEC Approved Byte-Wide Pinout
DESCRIPTION
The X28HC64 is an 8K x 8 E2PROM, fabricated with
Xicor’s proprietary, high performance, floating gate
CMOS technology. Like all Xicor programmable non-
volatile memories the X28HC64 is a 5V only device. The
X28HC64 features the JEDEC approved pinout for byte-
wide memories, compatible with industry standard RAMs.
The X28HC64 supports a 64-byte page write operation,
effectively providing a 32µs/byte write cycle and en-
abling the entire memory to be typically written in 0.25
seconds. The X28HC64 also features DATA Polling and
Toggle Bit Polling, two methods providing early end of
write detection. In addition, the X28HC64 includes a
user-optional software data protection mode that further
enhances Xicor’s hardware write protect capability.
Xicor E2PROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data re-
tention is greater than 100 years.
PIN CONFIGURATIONS
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
PLASTIC DIP
FLAT PACK
CERDIP
SOIC
1 28
2 27
3 26
4 25
5 24
6 23
7 22
X28HC64
8 21
9 20
10 19
11 18
12 17
13 16
14 15
VCC
WE
NC
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/04
I/O3
3857 FHD F02.1
LCC
PLCC
4 3 2 1 32 31 30
A6 5
29 A8
A5 6
28 A9
A4 7
27 A11
A3 8
A2 9
X28HC64
26 NC
25 OE
A1 10
24 A10
A0 11
23 CE
NC 12
22 I/O7
I/O0 13
21 I/O6
14 15 16 17 18 19 20
3857 FHD F03
A2
A1
A0
I/O0
I/O1
I/O2
NC
VSS
NC
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TSOP
X28HC64
32 A3
31 A4
30 A5
29 A6
28 A7
27 A12
26 NC
25 NC
24 VCC
23 NC
22 WE
21 NC
20 A8
19 A9
18 A11
17 OE
PGA
3857 ILL F22
I/O1 I/O2 I/O3 I/O5 I/O6
12 13 15 17 18
I/O0 A0
VSS I/O4 I/O7
11 10 14 16 19
A1 A2
98
CE A10
20 21
X28HC64
A3 A4
OE A11
76
22 23
A5 A12 VCC A9 A8
5 2 28 24 25
A6 A7 NC WE NC
4 3 1 27 26
BOTTOM VIEW
3857 FHD F04
© Xicor, Inc. 1994, 1995, 1996 Patents Pending
3857-3.0 8/5/97 T1/C0/D0 EW
1
Characteristics subject to change without notice
X28HC64
DATA POLLING I/O7
Figure 2. DATA Polling Bus Sequence
LAST
WE WRITE
CE
OE
VIH
I/O7
A0–A12
An
HIGH Z
VOL
An An
An
An
VOH
X28HC64
READY
An An
3857 FHD F12
Figure 3. DATA Polling Software Flow
WRITE DATA
DATA Polling can effectively reduce the time for writing
to the X28HC64. The timing diagram in Figure 2 illus-
trates the sequence of events on the bus. The software
flow diagram in Figure 3 illustrates one method of
implementing the routine.
WRITES
COMPLETE?
NO
YES
SAVE LAST DATA
AND ADDRESS
READ LAST
ADDRESS
IO7
COMPARE?
YES
NO
READY
3857 FHD F13
4
4페이지 X28HC64
SOFTWARE DATA PROTECTION
Figure 6. Timing Sequence—Byte or Page Write
VCC
0V
DATA
ADDR
CE
AA
1555
55
0AAA
WE
A0
1555
WRITES
OK
tWC
≤tBLC MAX
BYTE
OR
PAGE
(VCC)
WRITE
PROTECTED
3857 FHD F16
Figure 7. Write Sequence for
Software Data Protection
WRITE DATA AA
TO ADDRESS
1555
WRITE DATA 55
TO ADDRESS
0AAA
WRITE DATA A0
TO ADDRESS
1555
WRITE DATA XX
TO ANY
ADDRESS
WRITE LAST
BYTE TO
LAST ADDRESS
BYTE/PAGE
LOAD ENABLED
OPTIONAL BYTE
OR PAGE WRITE
ALLOWED
Regardless of whether the device has previously been
protected or not, once the software data protection
algorithm is used, the X28HC64 will automatically dis-
able further writes unless another command is issued to
deactivate it. If no further commands are issued the
X28HC64 will be write protected during power-down
and after any subsequent power-up.
Note: Once initiated, the sequence of write operations
should not be interrupted.
AFTER tWC
RE-ENTERS DATA
PROTECTED STATE
3857 FHD F17
7
7페이지 | |||
구 성 | 총 24 페이지수 | ||
다운로드 | [ X28HC64S-70.PDF 데이터시트 ] |
당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는 |
구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
X28HC64S-70 | 5 Volt/ Byte Alterable E2PROM | Xicor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |