X28VC256KM-55 Datasheet PDF - Xicor
| Part Number | X28VC256KM-55 | |
| Description | 5 Volt/ Byte Alterable E2PROM | |
| Manufacturers | Xicor | |
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There is a preview and X28VC256KM-55 download ( pdf file ) link at the bottom of this page. Total 24 Pages | ||
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X28VC256
256K
X28VC256
5 Volt, Byte Alterable E2PROM
32K x 8 Bit
FEATURES
• Access Time: 45ns
• Simple Byte and Page Write
—Single 5V Supply
— No External High Voltages or VPP Control
Circuits
— Self-Timed
— No Erase Before Write
— No Complex Programming Algorithms
—No Overerase Problem
• Low Power CMOS:
—Active: 80mA
—Standby: 10mA
• Software Data Protection
—Protects Data Against System Level
Inadvertent Writes
• High Speed Page Write Capability
• Highly Reliable Direct Write™ Cell
—Endurance: 100,000 Write Cycles
—Data Retention: 100 Years
• Early End of Write Detection
—DATA Polling
—Toggle Bit Polling
PIN CONFIGURATION
DESCRIPTION
The X28VC256 is a second generation high perfor-
mance CMOS 32K x 8 E2PROM. It is fabricated with
Xicor’s proprietary, textured poly floating gate tech-
nology, providing a highly reliable 5 Volt only nonvolatile
memory.
The X28VC256 supports a 128-byte page write opera-
tion, effectively providing a 24µs/byte write cycle and
enabling the entire memory to be typically rewritten in
less than 0.8 seconds. The X28VC256 also features
DATA Polling and Toggle Bit Polling, two methods of
providing early end of write detection. The X28VC256
also supports the JEDEC standard Software Data Pro-
tection feature for protecting against inadvertent writes
during power-up and power-down.
Endurance for the X28VC256 is specified as a minimum
100,000 write cycles per byte and an inherent data
retention of 100 years.
PLASTIC DIP
CERDIP
FLAT PACK
SOIC
LCC
PLCC
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1 28
2 27
3 26
4 25
5 24
6 23
7 22
X28VC256
8 21
9 20
10 19
11 18
12 17
13 16
14 15
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/04
I/O3
3869 FHD F02
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
4 3 2 1 32 31 30
5 29
6 28
7 27
8 26
9
X28VC256
25
10 24
11 23
12 22
13 21
14 15 16 17 18 19 20
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
3869 FHD F03
A2
A1
A0
I/O0
I/O1
I/O2
NC
VSS
NC
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TSOP
X28VC256
32 A3
31 A4
30 A5
29 A6
28 A7
27 A12
26 A14
25 NC
24 VCC
23 NC
22 WE
21 A13
20 A8
19 A9
18 A11
17 OE
3869 ILL F22
©Xicor, Inc. 1991, 1995 Patents Pending
3869-2.6 4/2/96 T4/C4/D0 NS
1 Characteristics subject to change without notice
|
| |
 
X28VC256
THE TOGGLE BIT I/O6
Figure 4. Toggle Bit Bus Sequence
LAST
WE WRITE
CE
OE
VOH
I/O6 * VOL
* I/O6 beginning and ending state of I/O6 will vary.
HIGH Z
*
X28VC256
READY
3869 FHD F14
Figure 5. Toggle Bit Software Flow
LAST WRITE
YES
LOAD ACCUM
FROM ADDR n
The Toggle Bit can eliminate the software housekeeping
chore of saving and fetching the last address and data
written to a device in order to implement DATA Polling.
This can be especially helpful in an array comprised of
multiple X28VC256 memories that is frequently up-
dated. The timing diagram in Figure 4 illustrates the
sequence of events on the bus. The software flow
diagram in Figure 5 illustrates a method for polling the
Toggle Bit.
COMPARE
ACCUM WITH
ADDR n
COMPARE
OK?
YES
X28VC256
READY
NO
3869 FHD F15
5
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for X28VC256KM-55 electronic component. |
| Information | Total 24 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ X28VC256KM-55.PDF Datasheet ] | |
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