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X3101 데이터시트 PDF




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부품번호 X3101 기능
기능 3 or 4 Cell Li-Ion Battery Protection and Monitor IC
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X3101 데이터시트, 핀배열, 회로
APPLICATION NOTE
A V A I LABLE
3 or 4 Cell Li-Ion BATTERY PACKS
PPrreelliimmiinnaarryy Information
X3100/X3101
4 cell / 3 cell
3 or 4 Cell Li-Ion Battery Protection and Monitor IC
FEATURE
• Software Selectable Protection Levels and
Variable Protect Detection/Release Times
• Integrated FET Drive Circuitry
• Cell Voltage and Current Monitoring
• 0.5% Accurate Voltage Regulator
• Integrated 4kbit EEPROM
• Flexible Power Management with 1µA Sleep
Mode
• Cell Balancing Control
BENEFIT
• Optimize protection for chosen cells to allow
maximum use of pack capacity.
• Reduce component count and cost
• Simplify implementation of gas gauge
• Accurate voltage and current measurements
• Record battery history to optimize gas gauge,
track pack failures and monitor system use
• Reduce power to extend battery life
• Increase battery capacity and improve cycle life
battery life
DESCRIPTION
The X3100 is a protection and monitor IC for use in
battery packs consisting of 4 series Lithium-Ion
battery cells. The X3101 is designed to work in 3 cell
applications. Both devices provide internal over-
charge, over-discharge, and over-current protection
circuitry, internal EEPROM memory, an internal
voltage regulator, and internal drive circuitry for
external FET devices that control cell charge,
discharge, and cell voltage balancing.
Over-charge, over-discharge, and over-current
thresholds reside in an internal EEPROM memory
register and are selected independently via software
using a 3MHz SPI serial interface. Detection and time-
out delays can also be individually varied using
external capacitors.
Using an internal analog multiplexer, the X3100 or
X3101 allow battery parameters such as cell voltage
and current (using a sense resistor) to be monitored
externally by a separate microcontroller with A/D
converter. Software on this microcontroller implements
gas gauge and cell balancing functionality in software.
The X3100 and X3101 contain a current sense
amplifier. Selectable gains of 10, 25, 80 and 160 allow
an external 10 bit A/D converter to achieve better
resolution than a more expensive 14 bit converter.
An internal 4kbit EEPROM memory featuring
IDLock, allows the designer to partition and “lock in”
written battery cell/pack data.
The X3100 and X3101 are each housed in a 28 Pin
TSSOP package.
FUNCTIONAL DIAGRAM
VCC RGP RGC RGO
UVP/OCP OVP/LMON
VCELL1
CB1
VCELL2
CB2
VCELL3
CB3
VCELL4/VSS
CB4
Over-charge
Over-discharge
Protection
Sense
Circuits
Protection
Sample Rate
Timer
Over-current
Protection &
Current Sense
5VDC
Regulator
FET Control
Circuitry
Internal Voltage Regulator
Power On reset &
Status Register
Protection Circuit
Timing Control
& Configuration
Configuration
Register
4 kbit
EEPROM
Control
Register
Analog
MUX
SPI
I/F
AS0
AS1
AS2
AO
S0
SCK
CS
SI
VSS
VCS1 VCS2 OVT UVT OCT
REV 1.1.8 12/10/02
www.xicor.com
Characteristics subject to change without notice. 1 of 40




X3101 pdf, 반도체, 판매, 대치품
X3100/X3101 – Preliminary Information
—Load Monitor (LMON)
In Over-current Protection mode, a small test current
(7.5µA typ.) is passed out of this pin to sense the load
resistance. The measured load resistance determines
whether or not the X3100 or X3101 returns from an
over-current protection mode (see section “Over-Current
Protection” on page 18).
Over-discharge (Under Voltage) Protection/
Over-current Protection (UVP/OCP):
Pin UVP/OCP controls the battery cell discharge via an
external power FET. This P-channel FET allows cell
discharge when UVP/OCP=Vss, and prevents cell
discharge when UVP/OCP=Vcc. The X3100 and X3101
turn the external power FET off when the X3100 or
X3101 detects either:
—Over-discharge Protection (UVP)
In this case, pin 24 is referred to as “Over-discharge
(Under-Voltage) protection (UVP)” (see section “Over-
discharge Protection” on page 15). UVP/OCP turns off
the FET to prevent damage to the battery cells by being
discharged to excessively low voltages.
—Over-current protection (OCP)
In this case, pin 24 is referred to as “Over-current
protection (OCP)” (see section “Over-Current Protection”
on page 18). UVP/OCP turns off the FET to prevent
damage to the battery pack caused by excessive current
drain (e.g. as in the case of a surge current resulting
from a stalled disk drive).
TYPICAL APPLICATION CIRCUIT
The X3100 and X3101 have been designed to operate
correctly when used as connected in the Typical
Application Circuit (see Figure 1 on page 5).
The power MOSFET’s Q1 and Q2 are referred to as the
“Discharge FET” and “Charge FET,” respectively. Since
these FETs are p-channel devices, they will be ON when
the gates are at VSS, and OFF when the gates are at
VCC. As their names imply, the discharge FET is used to
control cell discharge, while the charge FET is used to
control cell charge. Diode D1 allows the battery cells to
receive charge even if the Discharge FET is OFF, while
diode D2 allows the cells to discharge even if the charge
FET is OFF. D1 and D2 are integral to the Power FETs. It
should be noted that the cells can neither charge nor
discharge if both the charge FET and discharge FET are
OFF.
Power to the X3100 or X3101 is applied to pin VCC via
diodes D6 and D7. These diodes allow the device to be
powered by the Li-Ion battery cells in normal operating
conditions, and allow the device to be powered by an
external source (such as a charger) via pin P+ when the
battery cells are being charged. These diodes should
have sufficient current and voltage ratings to handle both
cases of battery cell charge and discharge.
The operation of the voltage regulator is described in
section “Voltage Regulator” on page 21. This regulator
provides a 5VDC±0.5% output. The capacitor (C1)
connected from RGO to ground provides some noise
filtering on the RGO output. The recommended value is
0.1µF or less. The value chosen must allow VRGO to
decay to 0.1V in 170ms or less when the X3100 or
X3101 enter the sleep mode. If the decay is slower than
this, a resistor (R1) can be placed in parallel with the
capacitor.
During an initial turn-on period (TPUR + TOC), VRGO has
a stable, regulated output in the range of 5VDC ± 10%
(see Figure 2). The selection of the microcontroller
should take this into consideration. At the end of this turn
on period, the X3100 and X3101 “self-tunes” the output
of the voltage regulator to 5V+/-0.5%. As such, VRGO
can be used as a reference voltage for the A/D converter
in the microcontroller. Repeated power up operations,
consistently re-apply the same “tuned” value for VRGO.
Figure 1 shows a battery pack temperature sensor
implemented as a simple resistive voltage divider,
utilizing a thermistor (RT) and resistor (RT’). The voltage
VT can be fed to the A/D input of a microcontroller and
used to measure and monitor the temperature of the
battery cells. RT’ should be chosen with consideration of
the dynamic resistance range of RT as well as the input
voltage range of the microcontroller A/D input. An output
of the microcontroller can be used to turn on the
thermistor divider to allow periodic turn-on of the sensor.
This reduces power consumption since the resistor
string is not always drawing current.
Diode D3 is included to facilitate load monitoring in an
Over-current protection mode (see section “Over-
Current Protection” on page 18), while preventing the
flow of current into pin OVP/LMON during normal
operation. The N-Channel transistor turns off this
function during the sleep mode.
Resistor RPU is connected across the gate and drain of
the charge FET (Q2). The discharge FET Q1 is turned
off by the X3100 or X3101, and hence the voltage at pin
OVP/LMON will be (at maximum) equal to the voltage of
the battery terminal, minus one forward biased diode
voltage drop (VP+–VD7). Since the drain of Q2 is
connected to a higher potential (VP+) a pull-up resistor
REV 1.1.8 12/10/02
www.xicor.com
Characteristics subject to change without notice. 4 of 40

4페이지










X3101 전자부품, 판매, 대치품
X3100/X3101 – Preliminary Information
Figure 2. Power Up Timing (Initial Power Up or after Sleep Mode)
TPUR
VCC
VSLR
0V
VRGO
0V
Voltage Regulator Output Status
(Internal Signal) VRGS
Over-current Detection Status
(Internal Signal) OCDS
Status Register Bit 0
VRGS+OCDS
Status Register Bit 2
(SWCEN=0) CCES+OVDS
Status Register Bit 2
(SWCEN=1)
OVDS
AS2_AS0
SPI PORT
5V±10% (Stable and Repeatable)
VRGO Tuned to 5V±0.5%
5V
2ms (Typ.)
1
TOC
0
1 1 = X3100/1 in Over-Current Protection Mode
0 = X3100/1 NOT in Over-Current Protection Mode
0
1 1 = X3100/1 in Over-Current Protection Mode OR VRGO Not Yet Tuned
0 = X3100/1 NOT in Over-Current Protection Mode AND VRGO Tuned
0
TOV+200ms
1
0
1 = VCELL < VCE OR X3100/1 in Over-charge Protection Mode
0 = VCELL > VCE OR X3100/1 NOT in Over-charge Protection Mode
1
0
1 = X3100/1 in Over-charge Protection Mode
0 = X3100/1 NOT in Over-charge Protection Mode
TOV+200ms OR TUV+200ms (whichever is longer)
Any Read or Write Operation, except
turn-on of FETs can start here.
Charge, Discharge FETs can be
turned on here.
REV 1.1.8 12/10/02
www.xicor.com
Characteristics subject to change without notice. 7 of 40

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