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X4003S8I-2.7A 데이터시트 PDF




Xicor에서 제조한 전자 부품 X4003S8I-2.7A은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 X4003S8I-2.7A 자료 제공

부품번호 X4003S8I-2.7A 기능
기능 CPU Supervisor
제조업체 Xicor
로고 Xicor 로고


X4003S8I-2.7A 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




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X4003S8I-2.7A 데이터시트, 핀배열, 회로
X4003/X4005
CPU Supervisor
FEATURES
• Selectable watchdog timer
—Select 200ms, 600ms, 1.4s, off
• Low VCC detection and reset assertion
—Five standard reset threshold voltages
nominal 4.62V, 4.38V, 2.92V, 2.68V, 1.75V
—Adjust low VCC reset threshold voltage using
special programming sequence
—Reset signal valid to VCC = 1V
• Low power CMOS
—12µA typical standby current, watchdog on
—800nA typical standby current watchdog off
—3mA active current
• 400kHz I2C interface
• 1.8V to 5.5V power supply operation
• Available packages
—8-lead SOIC
—8-lead MSOP
BLOCK DIAGRAM
DESCRIPTION
These devices combine three popular functions, Power-
on Reset Control, Watchdog Timer, and Supply Voltage
Supervision. This combination lowers system cost,
reduces board space requirements, and increases
reliability.
Applying power to the device activates the power on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent
protection mechanism for microcontrollers. When the
microcontroller fails to restart a timer within a select-
able time out interval, the device activates the RESET/
RESET signal. The user selects the interval from three
preset values. Once selected, the interval does not
change, even after cycling the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting the
system when VCC falls below the minimum VCC trip
point. RESET/RESET is asserted until VCC returns to
proper operating level and stabilizes. Five industry stan-
dard VTRIP thresholds are available; however, Xicor’s
unique circuits allow the threshold to be reprogrammed
to meet custom requirements, or to fine-tune the thresh-
old for applications requiring higher precision.
WP
SDA
SCL
VCC
Watchdog Transition
Detector
Data
Register
Command
Decode &
Control
Logic
VCC Threshold
Reset logic
Control
Register
VTRIP
+
-
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
Power on and
Low Voltage
Reset
Generation
RESET (X4003)
RESET (X4005)
REV 1.1.3 4/30/02
www.xicor.com
Characteristics subject to change without notice. 1 of 18




X4003S8I-2.7A pdf, 반도체, 판매, 대치품
X4003/X4005
To set the new VTRIP voltage, apply the desired VTRIP
threshold voltage to the VCC pin and tie the WP pin to
the programming voltage VP. Then write data 00hto
address 01h. The stop bit following a valid write operation
initiates the VTRIP programing sequence. Bring WP
LOW to complete the operation.
Resetting the VTRIP Voltage
This procedure is used to set the VTRIP to a “native”
voltage level. For example, if the current VTRIP is 4.4V
and the new VTRIP must be 4.0V, then the VTRIP must
be reset. When VTRIP is reset, the new VTRIP is some-
thing less than 1.7V. This procedure must be used to
set the voltage to a lower value.
To reset the new VTRIP voltage, apply the desired
VTRIP threshold voltage to the VCC pin and tie the WP
pin to the programming voltage VP. Then write 00h to
address 03h. The stop bit of a valid write operation ini-
tiates the VTRIP programming sequence. Bring WP
LOW to complete the operation.
Figure 2. Reset VTRIP Level Sequence (VCC > 3V. WP = 15-18V)
WP VP = 15-18V
0 1 23 4 56 7
0 1 23 4 56 7
0 1 23 4 56 7
SCL
SDA
A0h
03h 00h
Figure 3. Sample VTRIP Reset Circuit
VTRIP
Adj.
4.7K
RESET/
RESET
18
27
3 X4003/05 6
45
VP
Adjust
Run
µC
SCL
SDA
REV 1.1.3 4/30/02
www.xicor.com
Characteristics subject to change without notice. 4 of 18

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X4003S8I-2.7A 전자부품, 판매, 대치품
X4003/X4005
Figure 5. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable
Data Change
Data Stable
Serial Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met. See
Figure 6.
Serial Stop Condition
All communications must be terminated by a stop condi-
tion, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the Standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus. See Figure 6.
Figure 6. Valid Start and Stop Conditions
SCL
SDA
Start
Stop
Serial Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle, the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data. Refer to Figure 7.
The device will respond with an acknowledge after rec-
ognition of a start condition and the correct contents of
the slave address byte. Acknowledge bits are also pro-
vided by the X4003/4005 after correct reception of the
control register address byte, after receiving the byte
written to the control register and after the second
slave address in a read question (See Figure 8 and
See Figure 9.)
REV 1.1.3 4/30/02
www.xicor.com
Characteristics subject to change without notice. 7 of 18

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관련 데이터시트

부품번호상세설명 및 기능제조사
X4003S8I-2.7

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