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X46402V8E-3.1 데이터시트 PDF




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부품번호 X46402V8E-3.1 기능
기능 Dual Voltage CPU Supervisor with 64K Password Protected EEPROM
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X46402V8E-3.1 데이터시트, 핀배열, 회로
Preliminary Information
64K X46402
Dual Voltage CPU Supervisor with 64K Password Protected EEPROM
FEATURES
• Dual Voltage Detection and Reset Assertion
—Low Vcc Monitor
—Low V2MON Monitor
—Low Vcc Block of EEPROM Writes
—RESET Signal Valid down to Vcc=1V
• Selectable Watchdog Timer
—150ms, 450ms, 1s, 5s, 10s, 20s, 1min, OFF
• Volatile Flag shows Watchdog/Low Voltage Reset
• 64kbit 2-wire Serial EEPROM
—1MHz Serial Interface speed
—64-Byte Page Write Mode
• Two 64-Byte OTP memory blocks
—Requires 64-bit OTP password to write
• Adjustable size Password Protected Array
—64 Bit Read and Write Array Passwords
—Non-password protected array area
• 8 count tamper counter for invalid passwords
• Operates at 2.5-3.7V
• 8L TSSOP package
DESCRIPTION
The X46402 combines several functions into one device.
The first is a dual voltage CPU supervisor plus 64Kbit
serial EEPROM memory with password protected write
and read operations. The size of the password protected
area is selectable by 3 control bits. A Write Protect (WP)
pin in conjunction with a WPEN bit provides hardware
OTP control of the configuration of the array. Password
protected areas require 64 bit read or write passwords
prior to access. The eighth illegal password entry
(regardless of the number of correct entries) sets an OTP
tamper bit. This bit is one of the 32 bits in the Device ID.
A secondary voltage monitor circuit activates a V2FAIL
pin when the secondary supply voltage drops below a
V2trip voltage. This circuit is primarily intended to detect
the immediate loss of the battery supply.
A low Vcc voltage detect circuit activates a RESET pin
when Vcc drops below a VTRIP voltage. This signal also
blocks read or write operations.
A watchdog timer with the time period controlled by three
bits provides several possible time out periods from
150ms to 1 minute.
Functional Diagram
WP
Write Control
Password Logic
HV Generation
Timing and Control
SCL
SDA
Command
Decode
and
Control
Logic
Write Password Area
(Bytes)
(64, 128, 256, 512,
2K, 4K, All, None)
No Password Area
Control
OTP array 1
OTP array 2
Passwords
(Vcc) Control Signal
Y Decoder
Data Register
©Xicor, Inc. 1994, 1995, 1996, 1998 Patents Pending
9900-3003 5 1/11/00 CM
1
WATCHDOG
TIMER RESET
RESET &
WATCHDOG
TIMEBASE
POWER ON AND
LOW VOLTAGE
RESET
GENERATION
RESET
+
- V2TRIP
+
- VTRIP
V2FAIL
V2MON
Vcc
Characteristics subject to change without notice




X46402V8E-3.1 pdf, 반도체, 판매, 대치품
X46402
Password Protection Configuration
Portions of the memory array may be “locked”. This area
of memory is password protected and is defined by the
bits BL2, BL1 and BL0. For these protected areas it is
necessary to use a Read password to output data and an
“Array Write” Password to write data. This block lock
area is re-writable, by issuing the correct password.
Table 2. Password Protected Block Size Select
BL2
BL1
BL0
000
001
010
011
100
101
110
111
Password Protected
Addresses
(Use Password
Command)
None
0000h - 003Fh
0000h - 007Fh
0000h - 00FFh
0000h - 01FFh
0000h - 07FFh
0000h - 0FFFh
0000h - 1FFFh
Non-Password
Protected Addresses
(Use Password or
No-Password Commands)
0000h - 1FFFh
0040h - 1FFFh
0080h - 1FFFh
0100h - 1FFFh
0200h - 1FFFh
0800h - 1FFFh
1000h - 1FFFh
None
SERIAL MEMORY OPERATION
There are four primary modes of operation for the
X46402; Protected READ and WRITE of the memory
and OTP arrays and unprotected Read and Write of non-
password protected areas of the memory array. Pro-
tected operations must be performed with one of four 8-
byte passwords.
The basic method of communication for the password
protected areas of the device is established by generat-
ing a start condition, then transmitting a command, fol-
lowed by the correct password. All parts will be shipped
from the factory with all passwords equal to ‘0’. The user
must perform ACK Polling to determine the validity of the
password, before starting a data transfer (see Acknowl-
edge Polling.) Only after the correct password is
accepted and a ACK polling has been performed, can
the data transfer occur.
Non-password protected areas of the memory array are
accessed in the same manner as access to password
protected areas, except the password and the password
acknowledge polling sequences are not required.
Data is transferred in 8-bit segments, with each transfer
being followed by an ACK, generated by the receiving
device.
Preliminary Information
If the X46402 is in a nonvolatile write cycle a “no ACK”
(SDA=HIGH) response will be issued in response to
loading of the command byte. If a stop is issued prior to
the start of a nonvolatile write cycle the write operation
will be terminated and the part will reset and enter into a
standby mode.
The basic sequence is illustrated in Figure 1.
After each transaction is completed, the X46402 will
reset and enter into a standby mode. This will also be the
response if an unsuccessful attempt is made to access a
protected array.
Password Protection
The X46402 requires a 64 bit write password to change
the contents of the control register or to write to a block
protected memory area. The X46402 also requires a 64
bit read password to output the contents of the block pro-
tected array or the control register. The block protection is
controlled by the [BL2:BL0] bits and allows the options
described in Table 2. If an area is block protected, it
needs a password prior to each read or write to the area.
The passwords cannot be read, even after the device
receives the correct password.
Figure 1. X46402 Device Operation (Password
Protected Areas)
LOAD COMMAND BYTE
LOAD 8-BYTE
PASSWORD
VERIFY PASSWORD
ACCEPTANCE BY
USE OF PASSWORD ACK POLLING
LOAD 2 BYTE ADDRESS
READ/WRITE
DATA BYTES
Twc OR DATA ACK POLLING
4

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X46402V8E-3.1 전자부품, 판매, 대치품
X46402
Preliminary Information
New Vcc or V2MON applied =
Old Vcc V2MON applied + Error
VTRIP/V2TRIP Programming
Execute
Reset VTRIP/V2TRIP
Sequence
Set Vcc = Vcc applied =
Desired VTRIP OR
Set V2MON = V2MON applied =
Desired V2TRIP,Vcc>=V2Trip
Execute
Set VTRIP,V2TRIP
Sequence
Recyle Vcc power
Apply 5V to Vcc or V2MON
Decrement Vcc
or V2MON
(<50mV step)
New Vcc/V2MON applied =
Old Vcc applied - Error
Execute
Reset V2TRIP,VTRIP
Sequence
NO RESET
or V2FAIL pin
goes active?
YES
Error < 0
Measured V(2)TRIP -
Desired V(2)TRIP
Error > 0
Error = 0
DONE
7

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