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X5045V14I PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 X5045V14I
기능 CPU Supervisor with 4K SPI EEPROM
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X5045V14I 데이터시트, 핀배열, 회로
4K
X5043/X5045
512 x 8 Bit
CPU Supervisor with 4K SPI EEPROM
FEATURES
• Selectable time out watchdog timer
• Low VCC detection and reset assertion
—Five standard reset threshold voltages
—Re-program low VCC reset threshold voltage
using special programming sequence.
—Reset signal valid to VCC = 1V
• Long battery life with low power consumption
—<50µA max standby current, watchdog on
—<10µA max standby current, watchdog off
—<2mA max active current during read
• 2.7V to 5.5V and 4.5V to 5.5V power supply
versions
• 4Kbits of EEPROM–1M write cycle endurance
• Save critical data with Block Lockmemory
—Protect 1/4, 1/2, all or none of EEPROM array
• Built-in inadvertent write protection
—Write enable latch
—Write protect pin
• 3.3MHz clock rate
• Minimize programming time
—16-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• SPI modes (0,0 & 1,1)
• Available packages
—8-lead MSOP, 8-lead SOIC, 8-pin PDIP
—14-lead TSSOP
DESCRIPTION
These devices combine four popular functions, Power-
on Reset Control, Watchdog Timer, Supply Voltage
Supervision, and Block Lock Protect Serial EEPROM
Memory in one package. This combination lowers
system cost, reduces board space requirements, and
increases reliability.
Applying power to the device activates the power on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscil-
lator to stabilize before the processor executes code.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the RESET/
RESET signal. The user selects the interval from three
preset values. Once selected, the interval does not
change, even after cycling the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting
the system when VCC falls below the minimum VCC
trip point. RESET/RESET is asserted until VCC returns
to proper operating level and stabilizes. Five industry
standard VTRIP thresholds are available, however,
Xicor’s unique circuits allow the threshold to be repro-
grammed to meet custom requirements or to fine-tune
the threshold for applications requiring higher precision.
BLOCK DIAGRAM
WP
SI
SO
SCK
CS/WDI
Data
Register
Command
Decode &
Control
Logic
VCC Threshold
Reset Logic
Watchdog Transition
Detector
Protect Logic
Status
Register
1Kbits
1Kbits
2Kbits
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
RESET/RESET
X5043 = RESET
X5045 = RESET
Power on and
VCC + Low Voltage
Reset
VTRIP
-
Generation
REV 1.1.2 5/29/01
www.xicor.com
Characteristics subject to change without notice. 1 of 20




X5045V14I pdf, 반도체, 판매, 대치품
X5043/X5045
Resetting the VTRIP Voltage
This procedure is used to set the VTRIP to a “native”
voltage level. For example, if the current VTRIP is 4.4V
and the new VTRIP must be 4.0V, then the VTRIP must
be reset. When VTRIP is reset, the new VTRIP is some-
thing less than 1.7V. This procedure must be used to
set the voltage to a lower value.
To reset the VTRIP voltage, apply at least 3V to the VCC
pin and tie the WP pin to the programming voltage VP.
Then send a WREN command, followed by a write of
Data 00h to address 03h. CS going HIGH on the write
operation initiates the VTRIP programming sequence.
Bring WP LOW to complete the operation.
Note: This operation also writes 00h to array address
03h.
Figure 2. Reset VTRIP Level Sequence (VCC > 3V. WP = 15–18V)
WP VPE = 15-18V
CS
SCK
0 1 23 4 56 7
SI
06h
WREN
Figure 3. Sample VTRIP Reset Circuit
VTRIP
Adj.
VP
Adjust
Run
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
8 Bits
02h
Write
03h
Address
18
2 X5043 7
3 X5045 6
45
4.7K
RESET
00h
Data
µC
SCK
SI
SO
CS
REV 1.1.2 5/29/01
www.xicor.com
Characteristics subject to change without notice. 4 of 20

4페이지










X5045V14I 전자부품, 판매, 대치품
X5043/X5045
Table 2. Device Protect Matrix
WREN CMD
(WEL)
0
x
1
Device Pin
(WP)
x
0
1
Memory Block
Protected Area
Unprotected Area
Protected
Protected
Protected
Protected
Protected
Writable
Figure 6. Read Status Register Sequence
CS
Status Register
(BL0, BL1, WD0, WD1)
Protected
Protected
Writable
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
SI
High Impedance
SO
Data Out
76543210
MSB
Figure 7. Write Status Register Sequence
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
SI
Data Byte
7 6 5 43 2 1 0
High Impedance
SO
Read Memory Array
When reading from the EEPROM memory array, CS is
first pulled low to select the device. The 8-bit READ
instruction is transmitted to the device, followed by the
8-bit address. Bit 3 of the READ instruction selects the
upper or lower half of the device. After the READ
opcode and address are sent, the data stored in the
memory at the selected address is shifted out on the
SO line. The data stored in memory at the next
address can be read sequentially by continuing to pro-
vide clock pulses. The address is automatically incre-
mented to the next higher address after each byte of
data is shifted out. When the highest address is
reached, the address counter rolls over to address
$000 allowing the read cycle to be continued indefi-
nitely. The read operation is terminated by taking CS
high. Refer to the Read EEPROM Array Sequence
(Figure 8).
REV 1.1.2 5/29/01
www.xicor.com
Characteristics subject to change without notice. 7 of 20

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