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X5083S8I-4.5A PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 X5083S8I-4.5A
기능 CPU Supervisor with 8Kbit SPI EEPROM
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X5083S8I-4.5A 데이터시트, 핀배열, 회로
X5083
CPU Supervisor with 8Kbit SPI EEPROM
FEATURES
• Low VCC detection and reset assertion
—Four standard reset threshold voltages
4.63V, 4.38V, 2.93V, 2.63V
—Re-program low VCC reset threshold voltage
using special programming sequence.
—Reset signal valid to VCC = 1V
• Selectable time out watchdog timer
• Long battery life with low power consumption
—<50µA max standby current, watchdog on
—<1µA max standby current, watchdog off
—<400µA max active current during read
• 8Kbits of EEPROM
• Save critical data with Block Lockmemory
—Block lock first or last page, any 1/4 or lower 1/2
of EEPROM array
• Built-in inadvertent write protection
—Write enable latch
—Write protect pin
• SPI Interface - 3.3MHz clock rate
• Minimize programming time
—16 byte page write mode
—5ms write cycle time (typical)
• SPI modes (0,0 & 1,1)
• Available packages
—8-lead TSSOP, 8-lead SOIC, 8-Lead PDIP
APPLICATIONS
• Communications Equipment
—Routers, Hubs, Switches
—Set Top Boxes
• Industrial Systems
—Process Control
—Intelligent Instrumentation
• Computer Systems
—Desktop Computers
—Network Servers
• Battery Powered Equipment
Typical Application
2.7-5.0V
VCC
X5083
RESET
CS
SCK
SI
SO
WP
VSS
VCC
uC
10K
RESET
SPI
VSS
BLOCK DIAGRAM
VCC
CS/WDI
SI
SO
SCK
WP
VTRIP
+
-
POR and Low
Voltage Reset
Generation
Reset & Watchdog
Timebase
Watchdog
Transition
Detector
Watchdog
Timer
Reset
Command
Decode &
Control
Logic
Protect Logic
Status
Register
EEPROM
Array
8Kbits
RESET (X5083)
X5083
Standard VTRIP Level
4.63V (+/-2.5%)
Suffix
-4.5A
4.38V (+/-2.5%)
-4.5
2.93V (+/-2.5%)
-2.7A
2.63V (+/-2.5%)
-2.7
See “Ordering Information” on page 21 for
more details
For Custom Settings, call Xicor.
REV 1.1.6 6/25/02
www.xicor.com
Characteristics subject to change without notice. 1 of 21




X5083S8I-4.5A pdf, 반도체, 판매, 대치품
X5083
Resetting the VTRIP Voltage
This procedure is used to set the VTRIP to a “native”
voltage level. For example, if the current VTRIP is 4.4V
and the new VTRIP must be 4.0V, then the VTRIP must
be reset. When VTRIP is reset, the new VTRIP is some-
thing less than 1.7V. This procedure must be used to
set the voltage to a lower value.
To reset the new VTRIP voltage, apply the desired
VTRIP threshold voltage to the Vcc pin and tie the WP
pin to the programming voltage VP. Then send a WREN
command, followed by a write of data 00h to address
03h. CS going HIGH on the write operation initiates the
VTRIP programming sequence. Bring WP LOW to com-
plete the operation.
Note: This operation also writes 00h to array address
03h.
Figure 2. Reset VTRIP Level Sequence (VCC > 3V. WP = 15–18V)
WP VP = 15-18V
CS
SCK
0 1 23 4 56 7
SI
06h
WREN
Figure 3. Sample VTRIP Reset Circuit
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23
02h
Write
16 Bits
0003h
Address
VTRIP
Adj.
VP
Adjust
Run
18
27
3 X5083 6
45
4.7K
RESET
00h
Data
µC
SCK
SI
SO
CS
REV 1.1.6 6/25/02
www.xicor.com
Characteristics subject to change without notice. 4 of 21

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X5083S8I-4.5A 전자부품, 판매, 대치품
X5083
Read Sequence
When reading from the EEPROM memory array, CS is
first pulled low to select the device. The 8-bit READ
instruction is transmitted to the device, followed by the
16-bit address. After the READ opcode and address
are sent, the data stored in the memory at the selected
address is shifted out on the SO line. The data stored
in memory at the next address can be read sequen-
tially by continuing to provide clock pulses. The
address is automatically incremented to the next
higher address after each byte of data is shifted out.
When the highest address is reached, the address
counter rolls over to address $0000 allowing the read
cycle to be continued indefinitely. The read operation is
terminated by taking CS high. Refer to the read
EEPROM array sequence (Figure 5).
To read the status register, the CS line is first pulled
low to select the device followed by the 8-bit RDSR
instruction. After the RDSR opcode is sent, the contents
of the status register are shifted out on the SO line.
Refer to the read status register sequence (Figure 6).
Write Sequence
Prior to any attempt to write data into the device, the
“Write Enable” Latch (WEL) must first be set by issuing
the WREN instruction (Figure 7). CS is first taken LOW,
then the WREN instruction is clocked into the device.
After all eight bits of the instruction are transmitted, CS
must then be taken HIGH. If the user continues the write
operation without taking CS HIGH after issuing the
WREN instruction, the write operation will be ignored.
To write data to the EEPROM memory array, the user
then issues the WRITE instruction followed by the 16
bit address and then the data to be written. Any
unused address bits are specified to be “0’s”. The
WRITE operation minimally takes 32 clocks. CS must
go low and remain low for the duration of the operation.
If the address counter reaches the end of a page and
the clock continues, the counter will roll back to the first
address of the same page and overwrite any data that
may have been previously written.
For a write operation (byte or page write) to be com-
pleted, CS can only be brought HIGH after bit 0 of the
last data byte to be written is clocked in. If it is brought
HIGH at any other time, the write operation will not be
completed (Figure 8).
To write to the status register, the WRSR instruction is
followed by the data to be written (Figure 9). Data bits
5, 6 and 7 must be “0”.
Read Status Operation
If there is not a nonvolatile write in progress, the read
status instruction returns the block lock setting from the
status register which contains the watchdog timer bits
WD1, WD0, and the block lock bits IDL2-IDL0 (Figure
6). The block lock bits define the block lock condition
(Table 1). The watchdog timer bits set the operation of
the watchdog timer (Table 2). The other bits are
reserved and will return ’0’ when read. See Figure 6.
During an internal nonvolatile write operaiton, the
Read Status Instruction returns a HIGH on SO in the
first bit following the RDSR instruction (the MSB). The
remaining bits in the output status byte are undefined.
Repeated Read Status Instructions return the MSB as
a ‘1’ until the nonvolatile write cycle is complete. When
the nonvolatile write cycle is completed, the RDSR
instruction returns a ‘0’ in the MSB position with the
remaining bits of the status register undefined. Subse-
quent RDSR instructions return the Status Register
Contents. See Figure 10.
RESET Operation
The RESET output is designed to go LOW whenever
VCC has dropped below the minimum trip point and/or
the watchdog timer has reached its programmable time
out limit.
The RESET output is an open drain output and
requires a pull up resistor.
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
– SO pin is high impedance.
– The write enable latch is reset.
– Reset signal is active for tPURST.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– A WREN instruction must be issued to set the write
enable latch.
– CS must come HIGH at the proper clock count in
order to start a nonvolatile write cycle.
– When VCC is below VTRIP, communications to the
device are inhibited.
REV 1.1.6 6/25/02
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