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X68C64 데이터시트 PDF




Xicor에서 제조한 전자 부품 X68C64은 전자 산업 및 응용 분야에서
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기능 E2 Micro-Peripheral
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X68C64 데이터시트, 핀배열, 회로
X686X8CX6M4icrocontroller Family Compatible
64K
X68C64
8192 x 8 Bit
E2 Micro-Peripheral
FEATURES
CONCURRENT READ WRITE
—Dual Plane Architecture
—Isolates Read/Write Functions
Between Planes
—Allows Continuous Execution of Code
From One Plane While Writing in
the Other Plane
Multiplexed Address/Data Bus
—Direct Interface to Popular 8-bit
Microcontrollers, e.g., Motorola M6801/03,
M68HC11 Family
High Performance CMOS
—Fast Access Time, 120ns
—Low Power
—60mA Maximum Active
—500µA Maximum Standby
Software Data Protection
Block Protect Register
—Individually Set Write Lock Out in 1K Blocks
Toggle Bit Polling
—Early End of Write Detection
Page Mode Write
—Allows up to 32 Bytes to be Written in
One Write Cycle
High Reliability
—Endurance: 100,000 Write Cycles
—Data Retention: 100 Years
DESCRIPTION
The X68C64 is an 8K x 8 E2PROM fabricated with
advanced CMOS Textured Poly Floating Gate Technol-
ogy. The X68C64 features a Multiplexed Address and
Data bus allowing a direct interface to a variety of
popular single-chip microcontrollers operating in ex-
panded multiplexed mode without the need for addi-
tional interface circuitry.
The X68C64 is internally configured as two independent
4K x 8 memory arrays. This feature provides the ability
to perform nonvolatile memory updates in one array and
continue operation out of code stored in the other array;
effectively eliminating the need for an auxiliary memory
device for code storage.
To write to the X68C64, a three-byte command
sequence must precede the byte(s) being written. The
X68C64 also provides a second generation software
data protection scheme called Block Protect. Block
Protect can provide write lockout of the entire device or
selected 1K blocks. There are eight 1K x 8 blocks that
can be write protected individually in any combination
required by the user. Block Protect, in addition to Write
Control input, allows the different segments of the memory
to have varying degrees of alterability in normal system
operation.
FUNCTIONAL DIAGRAM
CE
R/W
E
SEL
A8–A11
AS
CONTROL
LOGIC
LX
AD
TE
CC
HO
ED
SE
WC
A12
SOFTWARE
DATA
PROTECT
A12
1K BYTES A12 1K BYTES
M
1K BYTES
1K BYTES
U
1K BYTES X 1K BYTES
1K BYTES
1K BYTES
Y DECODE
CONCURRENT READ WRITEis a trademark of Xicor, Inc.
© Xicor, Inc. 1991, 1995, 1996 Patents Pending
3868-2.6 9/16/96 T0/C0/D2 SH
I/O & ADDRESS LATCHES AND BUFFERS
A/D0–A/D7
3868 FHD F02
1 Characteristics subject to change without notice




X68C64 pdf, 반도체, 판매, 대치품
X68C64
MODE SELECTION
CE E R/W Mode I/O
Power
VSS
LOW
HIGH
HIGH
X
X
HIGH
X
X
HIGH
LOW
Standby
Standby
Read
Write
High Z
High Z
DOUT
DIN
Standby (CMOS)
Standby (TTL)
Active
Active
3868 PGM T02.1
PAGE WRITE OPERATION
Regardless of the microcontroller employed, the X68C64
supports page mode write operations. This allows the
microcontroller to write from one to thirty-two bytes of
data to the X68C64. Each individual write within a page
write operation must conform to the byte write timing
requirements. The rising edge of E starts a timer delay-
ing the internal programming cycle 100µs. Therefore,
each successive write operation must begin within 100µs
of the last byte written. The following waveforms illus-
trate the sequence and timing requirements.
Page Write Timing Sequence for E Controlled Operation
OPERATION
CE
BYTE 0
BYTE 1
BYTE 2
LAST BYTE
READ (1)(2)
AFTER tWC READY FOR
NEXT WRITE OPERATION
AS
A/D0–A/D7
A8–A12
AIN DIN
A12=n
AIN DIN
A12=n
AIN DIN
A12=n
AIN DIN
A12=n
AIN DIN
A12=x
AIN
ADDR
AIN
Next Address
E
R/W
tBLC
tWC
3868 FHD F07
Notes: (1) For each successive write within a page write cycle A5–A12 must be the same.
(2) Although it is not illustrated, the microcontroller may interleave read operations between the individual byte writes within the page
write operation. Two responses are possible.
a. Reading from the same plane being written (A12 of Read = A12 of Write) is effectively a Toggle Bit Polling operation.
b. Reading from the opposite plane being written (A12 of Read A12 of Write) true data will be returned, facilitating the use of a
single memory component as both program and data storage.
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X68C64 전자부품, 판매, 대치품
X68C64
ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias .................. –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to VSS .................................. –1V to +7V
D.C. Output Current ............................................. 5mA
Lead Temperature
(Soldering, 10 seconds) .............................. 300°C
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reli-
ability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Supply Voltage
Limits
Commercial
0°C
+70°C
X68C64
5V ±10%
Industrial
–40°C
+85°C
3868 PGM T04.1
Military
–55°C
+125°C
3868 PGM T03.1
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Symbol
Parameter
Limits
Min.
Max.
Units
Test Conditions
ICC VCC Current (Active)
ISB1(CMOS) VCC Current (Standby)
ISB2(TTL) VCC Current (Standby)
ILI
ILO
VlL(1)
VIH(1)
VOL
VOH
Input Leakage Current
Output Leakage Current
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
–1
2
2.4
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V
Symbol
Test
60 mA
500 µA
6 mA
10
10
0.8
VCC + 0.5
0.4
µA
µA
V
V
V
V
Max.
CE = VIL, All I/O’s = Open,
Other Inputs = VCC, AS = VIH
CE = VSS, All I/O’s = Open,Other
Inputs = VCC – 0.3V, AS = VSS
CE = VIH, All I/O’s = Open, Other
Inputs = VIH, AS = VIL
VIN = VSS to VCC
VOUT = VSS to VCC, E = VIL
IOL = 2.1mA
IOH = –400µA
3868 PGM T05.1
Units
Conditions
CI/O(2)
CIN(2)
POWER-UP TIMING
Input/Output Capacitance
Input Capacitance
10 pF
6 pF
VI/O = 0V
VIN = 0V
3868 PGM T06
Symbol
Parameter
Max.
Units
tPUR(2)
tPUW(2)
Power-Up to Read
Power-Up to Write
Notes: (1) VIL min. and VIH max. are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
1
5
ms
ms
3868 PGM T07
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