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X68C75LI 데이터시트 PDF




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부품번호 X68C75LI 기능
기능 Port Expander and E2 Memory
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X68C75LI 데이터시트, 핀배열, 회로
APPLICATION NOTES
AVA I L A B L E
X68C7AN562S• ALNI6C4 •®ANE662 • AN74
SLIC X68C75 SLIC® E2 Microperipheral
Port Expander and E2 Memory
FEATURES
• Highly Integrated Microcontroller Peripheral
—8K x 8 E2 Memory
—2 x 8 General Purpose Bidirectional I/O Ports
—16 x 8 General Purpose Registers
—Integerated Interrupt Controller Module
—Internal Programmable Address Decoding
• Self Loading Integrated Code (SLIC)
—On-Chip BIOS and Boot Loader
—IBM/PC Based Interface Software(XSLIC)
• Concurrent Read During Write
—Dual Plane Architecture
• Isolates Read/Write Functions Between
Planes
• Allows Continuous Execution Of Code
From One Plane While Writing In The
Other Plane
• Multiplexed Address/Data Bus
—Direct Interface to Popular 68HC11 Family of
Microcontrollers
• Software Data Protection
—Protect Entire Array During Power-up/-down
• Block Lock™ Data Protection
—Set Write Lockout in 1K Blocks
• Toggle Bit Polling
• High Performance CMOS
—Fast Access Time, 120ns
—Low Power
• 60mA Active
• 100µA Standby
• PDIP, PLCC, and TQFP Packaging Available
DESCRIPTION
The X68C75 is a highly integrated peripheral for the
68HC11 family of microcontrollers. The device inte-
grates 8K-bytes of 5V byte-alterable nonvolatile memory,
2 bidirectional 8-bit ports, 16 general purpose registers,
programmable internal address decoding and a multi-
plexed address and data bus.
The 5V byte-alterable nonvolatile memory can be used
as program storage, data storage, or a combination of
both. The memory array is separated into two 4K-byte
sections which allows read accesses to one section
while a write operation is taking place in the other
section. The nonvolatile memory also features Software
Data Protection to protect the contents during power
transitions, and an advanced Block Protect register
which allows individual blocks of the memory to be
configured as read-only or read/write.
PIN CONFIGURATIONS
DIP
RESET
A12
WC
SEL
STRA
A15
NC
A14
A13
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
NC
A/D0
A/D1
A/D2
A/D3
A/D4
VSS
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40
10 39
11 38
12 37
X68C75
13 36
14 35
15 34
16 33
17 32
18 31
19 30
20 29
21 28
22 27
23 26
24 25
VCC
R/W
AS
A8
A9
A11
NC
IRQ
STRB
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
NC
E
A10
CE
A/D7
A/D6
A/D5
2899 ILL F01
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
2899-2.1 4/11/97 T0/C0/D1 SH
PLCC
TQFP
INDEX
CORNER
A14
A13
PA7
PA6
PA5
PA44
PA3
33
PA2
PA1
PA0
A/D0
6 5 4 3 2 1 44 43 42 41 40
7 39
8 38
9 37
10 36
11 X68C75 35
12 SLIC 34
13 33
14 32
15 31
16 30
17 29
18 19 20 21 22 23 24 25 26 27 28
A11
IRQ
STRB
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
2899 ILL F02.3
Concurrent Read During Write, Block Lock, and SLIC® E2 are registered trademarks of Xicor, Inc.
1 Characteristics subject to change without notice




X68C75LI pdf, 반도체, 판매, 대치품
X68C75 SLIC® E2
determine the early completion of a write cycle. During
the internal programming cycle, I/O6 will toggle from “1”
to “0” and “0” to “1” on subsequent attempts to read from
the memory plane that is being updated. When the
internal cycle is complete, the toggling will cease and the
device will be accessible for additional read or write
operations. Due to the dual plane architecture, reads for
polling must occur from the plane that was written; that
is, the state of A12 during a write must match the state of
A12 during polling.
DATA PROTECTION
The X68C75 provides two levels of data protection
through software control. There is a global software data
protection feature similar to the industry standard for
E2PROMs and a new Block Lock Protect write lockout
protection providing a secondary level data security
option.
Figure 1. Toggle Bit Polling E Control
OPERATION
LAST BYTE
WRITTEN
I/O6=X
I/O6=X
I/O6=X
I/O6=X
X68C75 READY FOR
NEXT OPERATION
CE
AS
A/D0–A/D7
A8–A12
AIN DIN
A12=n
AIN DOUT
A12=n
AIN DOUT
A12=n
AIN DOUT
A12=n
AIN DOUT
A12=n
AIN
ADDR
E
R/W
2899 ILL F05
4

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X68C75LI 전자부품, 판매, 대치품
X68C75 SLIC® E2
Figure 7. On-Chip Registers
76543210
0400
1
0
A15 A14 A13 A12 A11 A10 SFRM*
Special Function Register
Memory Map Register
0408 MSB
LSB PDRB
Port Data Register B
0410 MSB
LSB PDRA
Port Data Register A
0418
INT INTA INTB ENA ENB ENEE 0 EOW ISR
Interrupt Status Register
0420 IRST 1 AWO BWO DIRA DIRB STRA STRB CR
Configuration Register
0428 MSB
LSB PPRB
Port Pin Register B
0430 MSB
LSB PPRA
Port Pin Register A
0438
0 LAM 0 RST A15 A14 A13 EEM*
E2 Memory Map Register
0600 MSB
LSB
16 Bytes General Purpose SRAM
060F MSB
LSB
NOTE: * The value returned by reading these registers is the complement
of the actual data. These registers are nonvolatile and a special SDP
sequence is used to alter their contents. All the other registers are
initialized by a valid reset input signal and when the device is power cycled.
2899 ILL F07.3C
7

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