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X76F041H 데이터시트 PDF




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부품번호 X76F041H 기능
기능 PASS TM SecureFlash
제조업체 Xicor
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X76F041H 데이터시트, 핀배열, 회로
APPLICATION NOTE
A V A I LABLE
AN83 • Development Tools XK76C
Password Access Security Supervisor
4K
X76F041
4 x 128 x 8 Bit
PASSTM SecureFlash
FEATURES
• 64-Bit Password Security
• Three Password Modes
—Secure Read Access
—Secure Write Access
—Secure Configuration Access
• Programmable Configuration
—Read, Write and Configuration Access
Passwords
—Multiple Array Access/Functionality
—Retry Register/Counter
• 8 Byte Sector Write
• (4) 1K Memory Arrays
• ISO Response to Reset
• Low Power CMOS
—50µA Standby Current
—3mA Active Current
• 1.8V to 3.6V or 5V “Univolt” Read and Program
Power Supply Versions
• High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
—ESD Protection: 2000V on All Pins
DESCRIPTION
The X76F041 is a password access security supervisor
device, containing four 128 x 8 bit SecureFlash arrays.
Access can be controlled by three 64-bit programmable
passwords, one for read operations, one for write opera-
tions and one for device configuration.
The X76F041 features a serial interface and software
protocol allowing operation on a simple two wire bus. The
bus signals are a clock input (SCL) and a bidirectional
data input and output (SDA). Access to the device is con-
trolled through a chip select input (CS), allowing any
number of devices to share the same bus.
The X76F041 also features a synchronous response to
reset; providing an automatic output of a pre-configured
32-bit data stream conforming to the ISO standard for
memory cards.
The X76F041 utilizes Xicor’s proprietary Direct WriteTM
cell, providing a minimum endurance of 100,000 cycles
per sector and a minimum data retention of 100 years.
FUNCTIONAL DIAGRAM
CS
SCL
SDA
RETRY
COUNTER
INTERFACE
LOGIC
RST
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
7002-2.2 4/30/97 T3/C0/D0 SH
CHIP
ENABLE
DATA
TRANSFER
ARRAY ACCESS
ENABLE
PASSWORD ARRAY AND
PASSWORD VERIFICATION
LOGIC
ISO RESET RESPONSE
DATA REGISTER
CONFIGURATION
REGISTER
1
000–07F
080–0FF
100–17F
180–1FF
(4) 16 x 64
SECUREFLASH
ARRAYS
7002 ILL F01
Characteristics subject to change without notice




X76F041H pdf, 반도체, 판매, 대치품
X76F041
Array Control
The four 1K arrays, are each programmable to different
levels of access and functionality. Each array can be pro-
grammed to require or not require the read/write pass-
words. The functional options are:
• Read and Write Access.
• Read access with all write operations locked out.
• Read access and program only (writing a “1” to a
“0”). If an attempt to change a “0” to a “1” occurs the
X76F041 will reset, issue a “no ACK” and enter the
standby power mode.
• No read or write access to the memory. Access only
through use of the configuration password.
Array Map
First ‘1k’
Second ‘1k’
Third ‘1k’
Fourth ‘1k’
Addresses 000
Addresses 080
Addresses 100
Addresses 180
07F (hex)
0FF (hex)
17F (hex)
1FF (hex)
High-order
Addresses
7002 ILL F04A
8 Bit Array Control Register 1
SECOND 1K
X2 Y2 Z2 T2
ACCESS
MSB
FUNCTION
FIRST 1K
X1 Y1 Z1 T1
ACCESS
FUNCTION
LSB
7002 ILL F05A
8 Bit Array Control Register 2
UPPER 1K
X4 Y4 Z4 T4
ACCESS
MSB
FUNCTION
THIRD 1K
X3 Y3 Z3 T3
ACCESS
FUNCTION
LSB
7002 ILL F05B
Functional Bits
ZT
00
10
01
11
FUNCTIONALITY
READ AND WRITE UNLIMITED
READ ONLY, WRITE LIMITED
PROGRAM & READ ONLY,
ERASE LIMITED
NO READ OR WRITE, FULLY
LIMITED
7002 FRM T02
Access Bits
XY
READ
PASSWORD
WRITE
PASSWORD
0 0 NOT REQUIRED NOT REQUIRED
1 0 NOT REQUIRED REQUIRED
0 1 REQUIRED NOT REQUIRED
1 1 REQUIRED
8-Bit Configuration Register
REQUIRED
7002 FRM T03
MSB
LSB
UA1 UA2 1
0 RCR RCE 0
0
RESERVED
RETRY COUNTER ENABLE
RETRY COUNTER RESET
RESERVED
RESERVED
UNAUTHORIZED ACCESS BIT 2
UNAUTHORIZED ACCESS BIT 1
7002 ILL F06
Unauthorized Access Bits (UA1, UA2):
10
Access is forbidden if retry register equals the retry
counter (provided that the retry counter is enabled) and
no further access of any kind will be allowed.
0 1, 0 0, 1 1
Only configuration operations are allowed if the retry reg-
ister equals the retry counter (provided that the retry
counter is enabled).
Retry Counter Reset Bit (RCR):
If the retry counter reset bit is a “1” then the retry counter
will be reset following a correct password, provided the
retry counter is enabled.
If the retry counter reset bit is a “0” then the retry counter
will not be reset following a correct password, provided
the retry counter is enabled.
Retry Counter Enable Bit (RCE):
If the Retry counter enable bit is a “1”, then the retry
counter is enabled. An initial comparison between the
retry register and retry counter determines whether the
number of allowed incorrect password attempts has
been reached. If not, the protocol continues and in case
of a wrong password, the retry counter is incremented by
one. If the password is correct then the retry counter will
either be reset or unchanged, depending on the reset bit.
4

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X76F041H 전자부품, 판매, 대치품
X76F041
WRITE OPERATION
Sector Write
The Sector Write mode requires issuing the 3-bit write
command followed by the address, password if required
and then the data bytes transferred as illustrated in Fig-
Figure 6. Sector Write
ure 6. Eight bytes must be transferred. After the last byte
to be transferred is acknowledged, a stop condition is
issued, which starts the nonvolatile write cycle. If more
than 8 bytes are transferred the data will wrap around
and previous data will be overwritten. All data will be writ-
ten to the same sector as defined by A8–A3.
SDA LINE
S
T
A
R
T
C
M
D
A
X
A
X
A
X
A
X
A
8
AAAAAAAA
76543210
WRITE
PASSWORD 7
S
A AA
C CC
K KK
IF PASSWORD
MATCH THEN
DATA 0
DATA 1
DATA 2
AAAA
CCCC
KKKK
WRITE
PASSWORD 0
A
C
K
DATA 7
WAIT
tWC/ACK POLLING
A
C
K
S
T
O
P WAIT
S tWC
A
C
K
7002 ILL F10.1
7

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