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X76F100S8 데이터시트 PDF




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부품번호 X76F100S8 기능
기능 1K 128 x 8 Bit
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X76F100S8 데이터시트, 핀배열, 회로
1K
X76F100
128 x 8 Bit
Secure SerialFlash
FEATURES
• 64-bit password security
• One array (112-bytes) two passwords (16-bytes)
—Read password
—Write password
• Programmable passwords
• Retry counter register
—Allows 8 tries before clearing of the array
• 32-bit response to reset (rst input)
• 8-byte sector Write Mode
• 1MHz clock rate
• 2-wire serial interface
• Low power CMOS
—3.0 to 5.5V operation
—Standby current less than 1µA
—Active current less than 3 mA
• High reliability endurance:
—100,000 write cycles
• Data retention: 100 years
• Available in:
—8-lead PDIP, SOIC, MSOP, and smart car module
DESCRIPTION
The X76F100 is a Password Access Security Supervi-
sor, containing one 896-bit Secure SerialFlash array.
Access to the memory array can be controlled by two
64-bit passwords. These passwords protect read and
write operations of the memory array.
The X76F100 features a serial interface and software
protocol allowing operation on a popular two wire bus.
The bus signals are a clock Input (SCL) and a bidirec-
tional data input and output (SDA). Access to the
device is controlled through a chip select (CS) input,
allowing any number of devices to share the same bus.
The X76F100 also features a synchronous response
to reset providing an automatic output of a hard-wired
32-bit data stream conforming to the industry standard
for memory cards.
The X76F100 utilizes Xicor’s proprietary Direct Write
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
BLOCK DIAGRAM
CS
SCL
SDA
Interface
Logic
RST
Chip Enable
Data Transfer
Array Access
Enable
Password Array
and Password
Verification Logic
Reset
Response Register
8K Byte
SerialFlash Array
Array 0
(Password Protected)
32 Byte
SerialFlash Array
Array 1
(Password Protected)
Retry Counter
REV 1.0 6/22/00
www.xicor.com
Characteristics subject to change without notice. 1 of 16




X76F100S8 pdf, 반도체, 판매, 대치품
X76F100
Figure 2. Data Validity
SCL
SDA
Data Stable
Data
Change
Figure 3. Definition of Start and Stop Conditions
SCL
SDA
Start Condition
Table 1. X76F100 Instruction Set
Command after Start
1 0 0 S3 S2 S1 S00
1 0 0 S3 S2 S1 S0 1
11111100
11111110
01010101
Stop Condition
Command Description
Sector Write
Sector Read
Change Write Password
Change Read Password
Password ACK Command
Password Used
Write
Read
Write
Write
None
Illegal command codes will be disregarded. The part
will respond with a “no-ACK” to the illegal byte and
then return to the standby mode. All write/read opera-
tions require a password.
PROGRAM OPERATIONS
Sector Write
The sector write mode requires issuing the 8-bit write
command followed by the password and then the data
bytes transferred as illustrated in Figure 4. The write
command byte contains the address of the sector to be
written. Data is written starting at the first address of a
sector and eight bytes must be transferred. After the
last byte to be transferred is acknowledged a stop con-
dition is issued which starts the nonvolatile write cycle.
If more or less than 8-bytes are transferred, the data in
the sector remains unchanged.
ACK Polling
Once a stop condition is issued to indicate the end of
the host’s write sequence, the X76F100 initiates the
internal nonvolatile write cycle. In order to take advan-
tage of the typical 5ms write cycle, ACK polling can
begin immediately. This involves issuing the start con-
dition followed by the new command code of 8-bits (1st
byte of the protocol.) If the X76F100 is still busy with
the nonvolatile write operation, it will issue a “no-ACK”
in response. If the nonvolatile write operation has com-
pleted, an “ACK” will be returned and the host can then
proceed with the rest of the protocol.
REV 1.0 6/22/00
www.xicor.com
Characteristics subject to change without notice. 4 of 16

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X76F100S8 전자부품, 판매, 대치품
X76F100
PASSWORDS
Passwords are changed by sending the “change read
password” or “change write password” commands in a
normal sector write operation. A full eight bytes con-
taining the new password must be sent, following suc-
cessful transmission of the current write password and
a valid password ACK response. The user can use a
repeated ACK Polling command to check that a new
password has been written correctly. An ACK indicates
that the new password is valid.
There is no way to read any of the passwords.
Response to Reset (Default = 19 00 AA 55)
The ISO Response to reset is controlled by the RST,
CS and CLK pins. When RST is pulsed high, while CS
is low, the device will output 32-bits of data, one bit per
clock. This conforms to the ISO standard for “synchro-
nous response to reset”. CS must remain LOW and the
part must not be in a write cycle for the response to
reset to occur.
After initiating a nonvolatile write cycle the RST pin
must not be pulsed until the nonvolatile write cycle is
complete. If not, the ISO response will not be acti-
vated. Also, any attempt to pulse the RST pin in the
middle of an ISO transaction will stop the transaction
with the SDA pin in high impedance. The user will have
to issue a stop condition and start the transaction
again. If at any time during the Response to Reset CS
goes HIGH, the response to reset will be aborted and
the part will return to the standby state. A Response to
Reset is not available during a nonvolatile write cycle.
Continued clocks after the 32-bits, will output the 32-bit
sequence again, starting at byte 0.
Figure 7. Response to RESET(RST)
CS
RST
SCK
SO 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0
Byte
LSB
MSB LSB
0
MSB LSB
MSB LSB
12
MSB
3
REV 1.0 6/22/00
www.xicor.com
Characteristics subject to change without notice. 7 of 16

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