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X76F640HE 데이터시트 PDF




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기능 Secure SerialFlash
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X76F640HE 데이터시트, 핀배열, 회로
64K
X76F640
8Kx8+32x8
Secure SerialFlash
FEATURES
• 64-bit Password Security
—Five 64-bit Passwords for Read, Program
and Reset
• 8192 Byte+32 Byte Password Protected Arrays
—Seperate Read Passwords
—Seperate Write Passwords
—Reset Password
• Programmable Passwords
• Retry Counter Register
—Allows 8 tries before clearing of both arrays
—Password Protected Reset
• 32-bit Response to Reset (RST Input)
• 32 byte Sector Program
• 400kHz Clock Rate
• 2 wire Serial Interface
• Low Power CMOS
—2.7 to 5.5V operation
—Standby current Less than 1µA
—Active current less than 3 mA
• High Reliability Endurance:
—100,000 Write Cycles
• Data Retention: 100 years
• Available in:
—8 lead SOIC
—SmartCard Module
DESCRIPTION
The X76F640 is a Password Access Security Supervisor,
containing one 65536-bit Secure SerialFlash array and
one 256-bit Secure SerialFlash array. Access to each
memory array is controlled by two 64-bit passwords.
These passwords protect read and write operations of
the memory array. A separate RESET password is used
to reset the passwords and clear the memory arrays in
the event the read and write passwords are lost.
The X76F640 features a serial interface and software
protocol allowing operation on a popular two wire bus.
The bus signals are a clock Input (SCL) and a bidirec-
tional data input and output (SDA). Access to the device
is controlled through a chip select (CS) input, allowing
any number of devices to share the same bus.
The X76F640 also features a synchronous response to
reset providing an automatic output of a hard-wired 32-bit
data stream conforming to the industry standard for
memory cards.
The X76F640 utilizes Xicor’s proprietary Direct WriteTM
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
Functional Diagram
CS
SCL
SDA
INTERFACE
LOGIC
RST
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
7025-1.4 3/24/97 T2/C0/D1 SH
CHIP ENABLE
DATA TRANSFER
ARRAY ACCESS
ENABLE
PASSWORD ARRAY
AND PASSWORD
VERIFICATION LOGIC
RESET
RESPONSE REGISTER
1
8K BYTE
SerialFlash ARRAY
ARRAY 0
(PASSWORD PROTECTED)
32 BYTE
SerialFlash ARRAY
ARRAY 1
(PASSWORD PROTECTED)
RETRY COUNTER
7025 FM 01
Characteristics subject to change without notice




X76F640HE pdf, 반도체, 판매, 대치품
X76F640
Figure 2. Data Validity
SCL
SDA
Data Stable
Data
Change
Figure 3. Definition of Start and Stop Conditions
7025 FM 04
SCL
SDA
Start Condition
Stop Condition
7025 FM 05
Table 1. X76F640 Instruction Set
1st Byte
after Start
1st Byte
after
Password
2nd Byte
after
Password
1000 0000 High Address Low address
1000 1000 High Address Low address
1001 0000 High Address Low address
1001 1000 High Address Low address
1010 0000 0000 0000 0000 0000
1010 1000 0000 0000 0000 0000
1011 0000 0000 0000
1011 1000 0000 0000
0000 0000
0000 0000
1100 0000 0000 0000
1110 0000 not used
0000 0000
not used
1110 1000 not used
not used
1111 0000
not used
All the rest
not used
Command Description
Read (Array 0)
Read (Array 1)
Sector Write (Array 0)
Sector Write (Array 1)
Change Read 0 Password
Change Read 1 Password
Change Write 0 Password
Change Write 1 Password
Change Reset Password
Reset Password Command
Reset Device Command
ACK Polling command (Ends Password operation)
Reserved
Password
used
Read 0
Read 1
Write 0
Write 1
Read 0
Read 1
Write 0
Write 1
Reset
Reset
Reset
None
7025 FM T04
Notes: Illegal command codes will be disregarded. The part will respond with a “no-ACK” to the illegal byte and then return to the standby mode.
All write/read operations require a password.
4

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X76F640HE 전자부품, 판매, 대치품
X76F640
Figure 5. Acknowledge Polling
SCL 8th clk.
of 8th
pwd. byte
‘ACK’
clk
8th ‘ACK’
clk clk
SDA
‘ACK’
START
condition
8th bit
ACK or
no ACK
7025 FM 10
READ OPERATIONS
Read operations are initiated in the same manner as write
operations but with a different command code.
Random Read
The master issues the start condition and a Read instruc-
tion and password, performs a Password Ack Polling, then
issues the word address. Once the password has been
acknowledged and first byte has been read, another start
can be issued followed by a new 8-bit address. Random
reads are allowed, but only the low order 8 bits can
change. This limits random reads to a 256 byte block.
Therefore, with a single password cycle only a 256 byte
block of array 0 may be accessed randomly. To randomly
access another block of array 0, a stop must be issued fol-
lowed by a new command/address/password sequence. A
random read of the array 1 can access all locations with-
out another password command sequence.
Figure 6. Random Read
COMMAND
Read
Password
7
SDA S
Sequential Read
The host can read sequentially within an array after the
password acceptance sequence. The data output is
sequential, with the data from address n followed by the
data from n+1. The address counter for read operations
increments all address bits, allowing the entire memory
array contents to be serially read during one operation. At
the end of the address space (address 1FFFh for array 0,
1Fh for array 1), the counter “rolls over” to address 0 and
the X76F640 continues to output data for each acknowl-
edge received. Refer to figure 7 for the address, acknowl-
edge and data transfer sequence. An acknowledge must
follow each 8-bit data transfer. After the last bit has been
read, a stop condition is generated without a preceding
acknowledge.
Read
Password
0
Wait tWC
OR
Repeated
ACK Polling
Command
If ACK, then
Password Matches
ACK POLLING
COMMAND
S
Data X
S
Data Y
S
7025 FM 11
7

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