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X84041SI 데이터시트 PDF




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부품번호 X84041SI 기능
기능 Micro Port Saver E2PROM
제조업체 Xicor
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X84041SI 데이터시트, 핀배열, 회로
APPLICATION NOTES AND DEVELOPMENT SYSTEM
AVA I L A B L E
X84041AN10 • AN17 • AN57 • XK84
4K X84041
Micro Port Saver E2PROM
MPSE2PROM
FEATURES
• Direct Interface to Micros
—Eliminates I/O port requirements
—No interface glue logic required
—Eliminates need for parallel to serial converters
• 3.3Mbps data transfer rate
• Low Power CMOS
—2.7V to 5.5V Operation
—Standby Current Less than 50µA
—Active Current Less than 1mA
• 45ns Read Access Time
• 8-Byte Page Write Mode
• Typical Nonvolatile Write Cycle Time: 5ms
• High Reliability
—100,000 Endurance Cycles
—Guaranteed Data Retention: 100 Years
• 8-Lead PDIP, 8-Lead SOIC, and
14-Lead TSSOP Packages
DESCRIPTION
The X84041 Micro Port Saver is a 4096-bit CMOS
E2PROM designed for a direct interface to port limited
microcontroller or I/O limited microprocessor designs.
The X84041 provides all of the benefits of serial memo-
ries, such as low cost, low power, low voltage operation,
and small package size, while featuring higher data
transfer rates and reduced interface code requirements—
without the need for a dedicated serial bus. The X84041
is organized as a 512 x 8, but is also suitable in 16-bit or
32-bit environments, due to the bit serial nature of the
interface.
The X84041 directly connects to the processor bus and
communicates over a single data line using a sequence
of standard bus read and write operations. This elimi-
nates the need for dedicated port pins, parallel to serial
converters, complicated ASIC implementations, or other
glue logic, lowering system cost.
PIN CONFIGURATION
CE
I/O
WP
VSS
DIP/SOIC
18
27
X84041
36
45
VCC
NC
OE
WE
2704 ILL F01.2
BLOCK DIAGRAM
WP
H.V. GENERATION
TIMING & CONTROL
CE
COMMAND
OE DECODE
AND
WE CONTROL
I/O LOGIC
X
DEC
EEPROM
ARRAY
512 x 8
TSSOP
CE 1
I/O 2
14 VCC
13 NC
NC 3
12 NC
NC 4 X84041 11 NC
NC 5
10 NC
WP 6
9 OE
VSS
7
8 WE
2704 ILL F02a.1
© Xicor, Inc. 1994, 1995, 1996 Patents Pending
2704-4.4 6/12/96 T3/C1/D0 NS
PIN NAMES
I/O Data Input/Output
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
WP Write Protect Input
VCC Supply Voltage
VSS Ground
NC No Connect
Y DECODE
DATA REGISTER
2704 ILL F02
2704 PGM T01
1 Characteristics subject to change without notice




X84041SI pdf, 반도체, 판매, 대치품
X84041
Figure 2. Write Sequence
CE
OE
WE
I/O (IN)
I/O (OUT)
"0"
X X X X X X X A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
"1"
"0"
RESET
LOAD ADDRESS
LOAD DATA
START
NONVOLATILE
WRITE
2704 ILL F04
Write Protection
The following circuitry has been included to prevent
inadvertent nonvolatile writes:
— The internal Write Enable latch is reset upon
power-up.
— A reset sequence must be issued to set the internal
write enable latch before starting a write sequence.
— A special “start nonvolatile write” command
sequence is required to start a nonvolatile write
cycle.
— The internal Write Enable latch is reset automatically
at the end of a nonvolatile write cycle.
— The internal Write Enable latch is reset and remains
reset as long as the WP pin is LOW, which blocks all
nonvolatile write cycles.
SYMBOL TABLE
WAVEFORM INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW to
HIGH
May change
from HIGH to
LOW
Don’t Care:
Changes
Allowed
N/A
Will change
from LOW to
HIGH
Will change
from HIGH to
LOW
Changing:
State Not
Known
Center Line
is High
Impedance
4

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X84041SI 전자부품, 판매, 대치품
X84041
EQUIVALENT A.C. LOAD CIRCUITS
5V
2.06K
OUTPUT
3.03K
30pF
3V
2.39K
OUTPUT
4.58K
30pF
2704 ILL F05.2
2704 ILL F05a.3
A.C. CHARACTERISTICS
(Over the recommended operating conditions, unless otherwise specified.)
Read Cycle Limits – X84041
Symbol Parameter
VCC = 5V ±10%
Min.
Max.
VCC = 3V ±10%
Min.
Max.
tRC
tCE
tOE
tLOW
tHIGH
tLZ(4)
tHZ(4)
tOLZ(4)
tOHZ(4)
tOH
tWES
tWEH
Read Cycle Time
CE Access Time
OE Access Time
CE LOW Time
CE HIGH Time
CE LOW to Output In Low Z
CE HIGH to Output In High Z
OE LOW to Output In Low Z
OE HIGH to Output In High Z
Output Hold from CE or OE HIGH
WE HIGH Setup Time
WE HIGH Hold Time
300
70
70
0
0
0
0
0
25
25
45
45
30
30
300
65
65
70
70
0
0 35
0
0 35
0
25
25
Notes: (4) Periodically sampled, but not 100% tested. tHZ and tOHZ are measured from the point where CE or OE goes
HIGH (whichever occurs first) to the time when I/O is no longer being driven into a 5pF load.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2704 PGM T09.3
7

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