X84129S14-1.8 Datasheet PDF - Xicor
| Part Number | X84129S14-1.8 | |
| Description | uPort Saver EEPROM | |
| Manufacturers | Xicor | |
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APPLICATION NOTE
A V A I LABLE
AN95 • AN103 • AN107
16K/64K/128K
X84161/641/129
µPort Saver EEPROM
MPS™ EEPROM
FEATURES
• Up to 10MHz data transfer rate
• 25ns Read Access Time
• Direct Interface to Microprocessors and
Microcontrollers
—Eliminates I/O port requirements
—No interface glue logic required
—Eliminates need for parallel to serial converters
• Low Power CMOS
—1.8V–3.6V, 2.5V–5.5V and 5V ±10% Versions
—Standby Current Less than 1µA
—Active Current Less than 1mA
• Byte or Page Write Capable
—32-Byte Page Write Mode
• Typical Nonvolatile Write Cycle Time: 2ms
• High Reliability
—100,000 Endurance Cycles
—Guaranteed Data Retention: 100 Years
DESCRIPTION
The µPort Saver memories need no serial ports or spe-
cial hardware and connect to the processor memory bus.
Replacing bytewide data memory, the µPort Saver uses
bytewide memory control functions, takes a fraction of
the board space and consumes much less power.
Replacing serial memories, the µPort Saver provides all
the serial benefits, such as low cost, low power, low volt-
age, and small package size while releasing I/Os for
more important uses.
The µPort Saver memory outputs data within 25ns of an
active read signal. This is less than the read access time
of most hosts and provides “no-wait-state” operation.
This prevents bottlenecks on the bus. With rates to 10
MHz, the µPort Saver supplies data faster than required
by most host read cycle specifications. This eliminates
the need for software NOPs.
The µPort Saver memories communicate over one line of
the data bus using a sequence of standard bus read and
write operations. This “bit serial” interface allows the
µPort Saver to work well in 8-bit, 16 bit, 32-bit, and 64-bit
systems.
A Write Protect (WP) pin prevents inadvertent writes to
the memory.
Xicor EEPROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data reten-
tion is greater than 100 years.
BLOCK DIAGRAM
System Connection
Ports
Saved
µP
µC
DSP
ASIC
RISC
P0/CS
P1/CLK
P2/DI
P3/DO
A15
A0
D7
D0
OE
WE
©Xicor, Inc. 1994, 1997Patents Pending
7008-1.2 8/26/97 T2/C0/D0 SH
Internal Block Diagram
MPS
WP H.V. GENERATION
TIMING & CONTROL
CE
COMMAND
I/O DECODE
OE
AND
CONTROL
LOGIC
WE
X
DEC
EEPROM
ARRAY
16K x 8
8K x 8
2K x 8
Y DECODE
DATA REGISTER
7008 FRM F02.1
1 Characteristics subject to change without notice
|
| |
 
X84161/641/129
Low Power Operation
The device enters an idle state, which draws minimal cur-
rent when:
—an illegal sequence is entered. The following are the
more common illegal sequences:
• Read/Write/Write—any time
• Read/Write ‘1’—When writing the address or
writing data.
• Write ‘1’—when reading data
• Read/Read/Write ‘1’—after data is written to
device, but before entering the NV write sequence.
—the device powers-up;
—a nonvolatile write operation completes.
While a sequential read is in progress, the device
remains in an active state. This state draws more current
than the idle state, but not as much as during a read
itself. To go back to the lowest power condition, an invalid
condition is created by writing a ‘1’ after the last bit of a
read operation.
Write Protection
The following circuitry has been included to prevent
inadvertent nonvolatile writes:
—The internal Write Enable latch is reset upon
power-up.
—A reset sequence must be issued to set the internal
write enable latch before starting a write sequence.
—A special “start nonvolatile write” command sequence
is required to start a nonvolatile write cycle.
—The internal Write Enable latch is reset automatically
at the end of a nonvolatile write cycle.
—The internal Write Enable latch is reset and remains
reset as long as the WP pin is LOW, which blocks all
nonvolatile write cycles.
—The internal Write Enable latch resets on an invalid
write operation.
SYMBOL TABLE
WAVEFORM INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW to
HIGH
May change
from HIGH to
LOW
Don’t Care:
Changes
Allowed
N/A
Will change
from LOW to
HIGH
Will change
from HIGH to
LOW
Changing:
State Not
Known
Center Line
is High
Impedance
5
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| Information | Total 18 Pages | |
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