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VP101-3BAGP 데이터시트 PDF




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부품번호 VP101-3BAGP 기능
기능 30/50MHz 8-BIT CMOS VIDEO DAC
제조업체 Zarlink Semiconductor Inc
로고 Zarlink Semiconductor Inc 로고


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VP101-3BAGP 데이터시트, 핀배열, 회로
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THIS DOCUMENT IS FOR MAINTENANCE
PURPOSES ONLY AND IS NOT
RECOMMENDED FOR NEW DESIGNS
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VP101-3BAGP pdf, 반도체, 판매, 대치품
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ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
As specified in recommended operating conditions.
DC CHARACTERISTICS
Parameter
Symbol
Min.
Value
Typ.
Max.
Units
Resolution (each DAC)
8
Bits
Accuracy (each DAC)
Integral linearity error
Differential linearity error
Grey scale error
Monotonicity
INL
DNL
±0.3
±0.3
±1%
guaranteed
±1
±1
±5%
LSB
LSB
% grey scale
Digital inputs
Input high voltage
Input low voltage
Input high current
Input low current
VIH 3.0
VIL AGND-0.3
IIH
IIL
VAA+0.3
1.2
+1
-1
V
V
µA
µA
Analog outputs
Grey scale current range
15 20 mA
255 LSB
Output currents
White level relative to blank level
17.69
19.06
20.40
mA
276 LSB
White level relative to black level
16.74
17.62
18.50
mA
255 LSB
Black level relative to blank level
0.95 1.44 1.90
mA
21 LSB
Blank level on IOR, IOB
www.DataSheet4U.comBlank level on IOG
0 5 50
0
6.29 7.62 8.96
mA
LSB
mA
111 LSB
Sync level on IOG
0 5 50 µA
LSB
LSB size
LSB 69.1
µA
DAC to DAC matching
2%
Output compliance
External VREF input current
Internal voltage reference
Internal VREF temperature coefficient
VOC
IREF
VREF
-0.5
1.14
1.20
40
+1.4
10
1.26
V
µA
V
ppm/°C
VP101
Conditions
binary
coding
RS-343A
tolerances
assumed
AC CHARACTERISTICS
Parameter
Symbol
VP101-5
Min. Typ. Max.
VP101-3
Min. Typ. Max.
Units
Conditions
Max clock rate
fmax
50
30
MHz
Data and control setup time
Data and control hold time
tSU
tH
6
2
8
2
ns
ns
Clock cycle time
Clock pulse width high time
Clock pulse width low time
tCYC
tCLKH
tCLKL
20
8
8
33.3
10
10
ns
ns
ns
Analog output delay
Analog output rise/fall time
Analog output settling time
Glitch energy
Analog output skew
tDLY
tVRF
tS
10
8
12
100
03
10 ns
9 ns
15 ns
100 pV-sec
03
ns
Pipeline delay
1 1 1 1 1 1 Clock
VAA supply current
IAA
120 175
100 140
mA at fmax, VAA = 5V
3
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VP101-3BAGP 전자부품, 판매, 대치품
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VP101
APPLICATION NOTES
RS-343A and RS-170 Video Generation
For generation of RS-343A compatible video levels it is
recommended that a doubly terminated 75load be used
with an RSET resistor value of approximately 542
Similarly for generation of RS-170-compatible video, it is
recommended that a singly terminated 75load be used
with an RSET value of about 774. If the VP101 is not driving
a large capacitive load, there will be negligible difference in
video quality between doubly terminated 75and singly
terminated 75loads.t
If driving a large capacitive load (load RC >1/20IIfc) it is
recommended that an output buffer with unloaded gain >2 be
used to drive a doubly terminated 75load.
COMP Resistor
To optimise the settling time of the VP101, a resistor
may be added in series between the COMP capacitor and
COMP pin. The series resistor damps inductive ringing on
COMP, thus improving settling time.
TIMING WAVEFORMS
Non-Video Applications
The VP101 may be used in non-video applications by
disabling the video specific control inputs. REF WHITE
should be a logic ‘0’ while BLANC and SYNC should be a
logic ‘1’. ISYNC should be connected to VAA or AGND. All
three outputs will have the same full scale output current.
The relationship between RSET and full scale output
current (IOUT) in this configuration is as follows:
Iout (mA) = 7968 X V−−REF(V) 255 LSBs
RSET ()
Note that 1 LSB VREF (V)
32 X RSET ()
With the data inputs at $00, there is a DC offset current (Imin)
defined as follows:
Imin (mA) = 656 X VR−−EF−−(V−−) 21 LSBs
RSET ()
Therefore the total full scale output current will be IOUT +
Imin. The REF WHITE input may optionally be used as a
‘force to full scale’ control.
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Fig.4 Input/output timing
NOTES
1. Output delay, tDLY, measured from the 50% point of the rising edge of CLOCK to the 50% point of full scale transition.
2. Settling time, ts, measured from the 50% point of full scale transition to the output remaining within ± 1 LSB.
3. Output rise/fall time, tVRF, measured between the 10% and 90% points of full scale transition.
6
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관련 데이터시트

부품번호상세설명 및 기능제조사
VP101-3BAGP

30/50MHz 8-BIT CMOS VIDEO DAC

Zarlink Semiconductor Inc
Zarlink Semiconductor Inc

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