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VP2611CGGH1R 데이터시트 PDF




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기능 H.261 Encoder
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VP2611CGGH1R 데이터시트, 핀배열, 회로
Supersedes June 1996 edition, DS3487 - 4.0
VP2611
VP2611
H.261 Encoder
DS3487 - 4.1 December 1998
FEATURES
s Fully integrated H261 video encoder
s Up to full CIF resolution and 30 Hz frame rates
s Inputs YUV data in 8 x 8 sub block format
s Outputs run length coded coefficients
s On chip motion vector estimator with +/-7 pixel search
window
s Addresses and control generated internally for DRAM
frame store
s QFP package
ASSOCIATED PRODUCTS
s VP510 Colour Space Converter
s VP520S CIF/QCIF Converter
s VP2612 Video Multiplexer
s VP2614 Video Demultiplexer
s VP2615 H.261 Decoder
DESCRIPTION
The VP2611 Video Compression Source Coder forms part
of a chip set used in video conferencing, video telephony and
multimedia applications. It produces data which conforms to
the H261 standard for video compression with rates between
64K and 2M bits per second. With a 27 MHz clock the device
will accept data produced to full CIF resolution at 30 Hz frame
rates. The pipeline latency through the device is only 3 macro
block periods.
The VP2611 contains all the elements necessary for the
compression algorithm. It incorporates a Motion Vector Esti-
mator which performs a +/- 7 pixel search. The decision to use
inter or intra frame compression is made by the device, and the
selected data blocks are read from the frame store. New or
difference data is then passed through a Discrete Cosine
Transformer and quantized. Data from the quantizer is also
inverse quantized and passed through an Inverse Discrete
Cosine Transformer. This re-constructed data is then written
to the frame store for use in the next frame period.This frame
store is managed by an internal DRAM controller, and no
external logic is needed.
The input data must be in YUV space, and must also
conform to the six sub blocks per macro block format defined
by H261. Any conversion from RGB format is performed by
the VP510 Colour Space Converter. Any reduction in spatial
resolution, down to CIF or QCIF requirements, is done by the
VP520 Three Channel Video Filter.
The quantized data is zig-zag scanned and run length
coded before being output, together with block information
and motion vectors.
R VP510
G COLOUR SPACE
CONVERTER
B
NTSC
PAL
COMP VIDEO
DECODER
VIDEO
SYNC
USER
INTERFACE
Y
Cr/Cb
VP520
3 CHANNEL
VIDEO FILTER
REQYUV
FRMIN
MBLK'S
ADDR
DATA
CIF FRAME
STORE
16 X128K
SYSTEM
CONTROLLER
VP2611
RLC DATA
INTEGRATED
VIDEO ENCODER FLAGS
CIF FRAME
STORE
16X128K
CCIR601 RESOLUTION
Y 720 X 288 Cr/Cb 360 x 288
Y 720 X 240 Cr/Cb 360 x 240
NTSC
PAL
CIF RESOLUTION
Y 352 X 288
Cr/Cb 176 x 144
VP2612
VIDEO
MULTIPLEXER
TX BUFFER
32K X 8
H261
BIT
STREAM
64kb to 2Mb/s
Fig 1 : Typical Video Conferencing Transmission System
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VP2611CGGH1R pdf, 반도체, 판매, 대치품
VP2611
Frame Store Manager
The previous picture is stored in an external CIF DRAM
frame store, which is connected by a glueless interface. The
internal Frame Store Manager controls all read, write, and
refresh operations to these DRAMs. No provision is made to
allow the use of smaller DRAM's, if only QCIF operation is
required.
During the coding of each macroblock columns of the
search window are read from these DRAMs, and finally the
"best fit" macroBlock is obtained. At the completion of coding
the fully processed new macroblock is written to the DRAM's,
after it has been decoded again. In this way the frame store
maintains a bit-accurate duplicate of the image seen by the
Decoder (excepting transmission errors).
Several configurations are possible to make the required
128Kx16 store. Two 64K x 16 DRAMs could be employed; in
this case use the default 1M DRAM mode when setting up the
chip. Otherwise, a single 256K x 16 DRAM or four 256K x 4
DRAMs could be used. In these last two cases use OE1 as
ADR8, RW1 as R/W, and do not connect RW2 and OE2. Also,
use the Setup instruction at the CPORT to put the device into
4M DRAM mode.
Table 1 details the critical timing parameters which the
external DRAM must meet with SYSCLK running at 27MHz.
Note that, if used at slower speeds, the requirements on the
DRAM timing are relaxed with the exception of refresh. The
number of refresh cycles the VP2611 produces is directly
proportional to the SYSCLK frequency.
Discrete Cosine Transform
This circuit performs a Discrete Cosine Transform on each
8x8 sub block, whether in inter or intra mode. In intra mode,
eight bit pixel data is used, with a ninth implied sign bit ( all pixel
data is positive ). In inter mode the difference between the
current and best fit previous block is used. This will be a two's
complement number. Twelve bit coefficients are produced by
the DCT, and passed on to the quantizer.
Quantize
This section quantizes the results of the DCT by dividing
the 12 bit output from the DCT with a host supplied value. The
5 bit quantization value supplied corresponds to division of the
12 bit coefficients ( range ± 2048 ) by values from 2 to 62, but
in steps of 2. This variable quantization strategy allows the
volume of data generated by the encoder to be adjusted
dynamically, depending on the fullness of the transmission
buffer. For H.261 applications it uses the quantisation value
provided at the control port during the previous Macroblock
period (or at some earlier time). An option is provided which
allows two quantisation values to be used, one for use with
inter coded macroblocks, and the other for use with intra
coded macroblocks.
As specified in H.261, the DC coefficient of an Intra coded
Block is treated differently and the 12 bit value is always
divided by 8.
When the quantization value is small, and the DCT coef-
ficient is large, there is a danger of overflow in the eight bit
output. To avoid this a clipping circuit is included at the output
of the quantizer, which saturates at the maximum values.
4
Zig Zag Scan
This is essentially an address generator which reorders
the DCT coefficients according to the standard zig-zag scan
pattern. This has the effect of concentrating the significant
coefficients at the beginning of the sub-block, improving the
efficiency of the Run Length Coder.
Run Length Coder
Each coefficient output from the zig zag scan is examined.
If it is non-zero, then the Run Length Coding circuit will pass
the coefficient magnitude to the output port along with its zero
count i.e. the number of zero magnitude coefficients preced-
ing it within the same 8x8 sub-block.
Inverse Quantize
This circuit replicates the operation of the inverse quan-
tizer in the decoder. It reconstructs the 12 bit DCT coefficients
from the 8 bit quantized inputs, using the 5 bit quantization
value. This is achieved using the following formulae.
If QUANT is odd :
REC = QUANT*(2*LEVEL+1) : LEVEL > 0
REC = QUANT*(2*LEVEL-1) : LEVEL < 0
If QUANT is even :
REC = QUANT*(2*LEVEL+1)-1 : LEVEL > 0
REC = QUANT*(2*LEVEL-1)+1 : LEVEL < 0
For Intra Coded DC Coefficients :
REC = 8*LEVEL
except if LEVEL=255 when REC=1024
If LEVEL=0 then REC=0 in all cases.
The reconstructed values (REC) are passed through a
Clipping Circuit in case of arithmetic overflow.
Thus, the Inverse Quantizer restores the DCT coefficients
to their original value but with quantisation error.
Inverse DCT
This circuit replicates the operation of the Inverse Cosine
Transform in the Decoder, and outputs 9 bit signed pixel data
(intra mode) or pixel difference data (inter mode). The IDCT
fully meets the CCITT specification.
Reconstruction Adder
In Inter Mode, the IDCT data is added to the best fit block
from the previous frame store. In Intra mode, the IDCT data is
simply added to zero. After the adder, the sign bit is removed
from the result to give 8 bit pixels. Clipping circuits ensure that
any pixels with values exceeding 255 are clipped to 255, and
any with negative values are clipped to zero (such values are
possible due to quantization noise).

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VP2611CGGH1R 전자부품, 판매, 대치품
VP2611
SCLK
DCLK
20ns max
25ns max
DATA FROM
VP2611
20ns max
DATA VALID
DMODE
3:0
DATA VALID
Fig 8: Timing diagram
GOB Number : At the start of each new macroblock, the
current GOB Number is output on DBUS3:0. (DBUS3 is
MSB).
MB Number : After the GOB Number, the macroblock
Number is output on DBUS5:0 (DBUS5 is MSB).
Coded Block Pattern : This byte contains a 6 bit linear code
that indicates which of the sub-blocks actually contain
coded data. DBUS6 will be high if sub-block 1 contains
coded data, through to DBUS 1 being high if sub-block 6
contains coded data. DBUS7 and DBUS0 are not used.
Note that if the macro block is not motion compensated
and the coded block pattern is all zero's, the fixed macro
block bit will be set in the control decisions byte.
Quant Value :The quantisation value used in processing the
current macroblock is output on DBUS4:0 (DBUS4 is
MSB). This represents an actual quantisation level be-
tween 2 and 62, in steps of 2 and as defined in H.261.
Horizontal MV : If motion compensation is used, the horizontal
component of the motion vector will be output on DBUS4:0
(DBUS4 is MSB). This 5 bit value represents a two's
complement number in the range +/-15
(although only vectors in the range -8 to +7 are currently
possible with the VP2611).
Vertical MV : If motion compensation is used, the vertical
component of the motion vector will be output on DBUS4:0
(DBUS4 is MSB). This 5 bit value represents a two's
complement number in the range ±15 ( although only
vectors in the range ±7 are currently possible with the
VP2611).
CBUS3:0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
INSTRUCTION
Input VAR Threshold
Reserved
Input Inter Quantiser
Input Intra Quantiser
Input Setup Data
Input Control Functions
Reserved
Reserved
Output GOB Number
Output MB Number
Reserved
Output Control Decisions
Output Setup Data
Reserved
Reserved
Overide internal clock doubler
Table 3 : CBUS Instruction Codes
Sub-block Number : An identifier for the run length coded
coefficients which are about to be made available. DBUS
2:0 contain the coded sub-block number from 1 to 6. All
zero sub-blocks will not be produced at the outputs, and
their corresponding numbers will not appear.
Zero Run Count : The number of zero valued coefficents
preceding the next non zero coefficient is available on
DBUS5:0 (DBUS5 is MSB). Normally, DBUS7:6 are low,
except to signify the end of a Sub-block, when they will
both be high. Zero Run Count is always followed by a
coefficient, even at the end of a sub-block.
RLC Coefficient : This byte contains the 8 bit coefficient value.
It will always be a non-zero value, except when the
previous Zero Run Count signalled the end of sub-Block.
A zero value is then possible since, as stated above, the
run count is always followed by a coefficient byte, which
may be zero if the last coefficient is zero.
Wait State : This indicates that no valid data is being output
from the DBUS port during this cycle. No DCLK is pro-
duced for this state.
Pins which are "not used" for certain functions will be
forced low.
This diagram shows a typical Sub-block being output from the VP2611.
DCLK
DMODE
DBUS
15 7
X2
8 9 15 8 9 15 8 9 15
0 4 X 1 -2 X 252 0 X
Both msb's are high showing end of block.
Fig 9: DBUS Timing
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부품번호상세설명 및 기능제조사
VP2611CGGH1R

H.261 Encoder

Mitel Networks Corporation
Mitel Networks Corporation

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