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부품번호 | VP3203 기능 |
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기능 | P-Channel Enhancement-Mode Vertical DMOS FETs | ||
제조업체 | Supertex Inc | ||
로고 | |||
전체 6 페이지수
VP3203
P-Channel Enhancement-Mode
Vertical DMOS FET
Features
► Free from secondary breakdown
► Low power drive requirement
► Ease of paralleling
► Low CISS and fast switching speeds
► High input impedance and high gain
► Excellent thermal stability
► Integral source-to-drain diode
Applications
General Description
The Supertex VP3203 is an enhancement-mode (normally-
off) transistor that utilizes a vertical DMOS structure
and Supertex’s well-proven silicon-gate manufacturing
process. This combination produces a device with the
power handling capabilities of bipolar transistors, and the
high input impedance and positive temperature coefficient
inherent in MOS devices. Characteristic of all MOS
structures, this device is free from thermal runaway and
thermally-induced secondary breakdown.
► Motor controls
► Converters
► Amplifiers
► Switches
► Power supply circuits
► Drivers (relays, hammers, solenoids, lamps,
memories, displays, bipolar transistors, etc.)
Supertex’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications where
very low threshold voltage, high breakdown voltage, high
input impedance, low input capacitance, and fast switching
speeds are desired.
Ordering Information
Device
TO-92
Package Options
TO-243AA (SOT-89)
VP3203
VP3203N3-G
VP3203N8-G
-G indicates package is RoHS compliant (‘Green’)
* Mil visual screening available.
Die*
VP3203ND
BVDSS/BVDGS
(V)
-30
RDS(ON)
(max)
(Ω)
0.6
Pin Configurations
ID(ON)
(min)
(A)
14.0
Absolute Maximum Ratings
Parameter
Value
Drain-to-source voltage
Drain-to-gate voltage
Gate-to-source voltage
BVDSS
BVDGS
±20V
Operating and storage temperature -55OC to +150OC
Soldering temperature*
300OC
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
* Distance of 1.6mm from case for 10 seconds.
DRAIN
SOURCE
GATE
TO-92 (N3)
DRAIN
SOURCE
DRAIN
GATE
TO-243AA (SOT-89) (N8)
Product Marking
SiVP YY = Year Sealed
3 2 0 3 WW = Week Sealed
YYWW
= “Green” Packaging
Package may or may not include the following marks: Si or
TO-92 (N3)
VP2LW W = Code for week sealed
= “Green” Packaging
Packages may or may not include the following marks: Si or
TO-243AA (SOT-89) (N8)
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Typical Performance Curves (cont.)
BVDSS Variation with Temperature
1.1
1.0
0.9
-50
-10
0 50 100
Tj (°C)
Transfer Characteristics
-8 TA = -55°C
-6 VDS = -25V
-4
25°C
125°C
150
-2
0
0 -2 -4 -6 -8 -10
VGS (volts)
Capacitance vs. Drain-to-Source Voltage
300
f = 1MHz
225
CISS
150
75
0
-0
COSS
CRSS
-10 -20
VDS (volts)
-30
VP3203
On-Resistance vs. Drain Current
2.0
1.6
VGS = -5V
1.2
VGS = -10V
0.8
0.4
0
0 -4 -8 -12 -16 -20
ID (amperes)
V(th) and RDS Variation with Temperature
1.4
RDS(ON) @ -10V, -3A
1.4
1.2 1.2
1.0 1.0
0.8 0.8
V(th) @ -10mA
0.6 0.6
-50 0 50 100 150
Tj (°C)
Gate Drive Dynamic Characteristics
-10
-8
VDS = -10V
-6
VDS = -20V
-4 335pF
-2
200 pF
0
01 2 3 4
QG (nanocoulombs)
5
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
4
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부품번호 | 상세설명 및 기능 | 제조사 |
VP3203 | P-Channel Enhancement-Mode Vertical DMOS FETs | Supertex Inc |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |