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VP5311B 데이터시트 PDF




Mitel Networks Corporation에서 제조한 전자 부품 VP5311B은 전자 산업 및 응용 분야에서
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부품번호 VP5311B 기능
기능 NTSC/PAL Digital Video Encoder
제조업체 Mitel Networks Corporation
로고 Mitel Networks Corporation 로고


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VP5311B 데이터시트, 핀배열, 회로
VP5311B/VP5511B
Supersedes DS4575 1.5 May 1997 version
NTSC/PAL Digital Video Encoder
Advance Information
DS4575 - 2.2 October 1998
The VP5311/VP5511 converts digital Y, Cr, Cb, data
into analog NTSC/PAL composite video and S-video signals.
The outputs are capable of driving doubly terminated 75
ohm loads with standard video levels.
The device accepts data inputs complying with CCIR
Recommendation 601 and 656. The data is time multiplexed
on an 8 bit bus at 27MHz and is formatted as Y, Cr, Y, Cb
(i.e. 4:2:2). The video blanking and sync information from
REC 656 is included in the data stream when the VP5311/
VP5511 is working in slave mode.
The output pixel rate is 27MHz and the input pixel rate
is half this frequency, i.e. 13.5MHz.
All necessary synchronisation signals are generated
internally when the device is operating in master mode. In
slave mode the device will lock to the TRS codes or the HS
and VS inputs.
PIN 64
The rise and fall times of sync, burst envelope and
video blanking are internally controlled to be within
composite video specifications.
Three digital to analog converters (DACs) are used to
convert the digital luminance, chrominance and composite
data into true analog signals. An internally generated
reference voltage provides the biasing for the DACs.
PIN
1
FEATURES
2
s
s
s
s
s
s
s
s
s
s
s
Converts Y, Cr, Cb data to analog composite video and
S-video
www.DataSheet4U.com
Supports CCIR recommendations 601 and 656
All digital video encoding
Selectable master/slave mode for sync signals
Switchable chrominance bandwidth
Switchable pedestal with gain compensation
SMPTE 170M NTSC or CCIR 624 PAL compatible
outputs
GENLOCK mode
Line 21 Closed Caption encoding
I2C bus serial microprocessor interface
VP5311B supports Macrovision anti-taping format Rev.
6.1, in PAL and Rev. 7.01 in NTSC.
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
APPLICATIONS
s Digital Cable TV
s Digital Satellite TV
s Multi-media
s Video games
s Karaoke
s Digital VCRs
18
19
20
21
22
23
24
25
ORDERING INFORMATION
VP5311B/CG/GP1N
VP5511B/CG/GP1N
26
27
28
29
30
31
32
PIN 1 GP64
Figure 1 Pin connections (top view)
FUNCTION
VDD
GND
D0 (VS I/O)
D1 (HS I/O)
D2 (FC0 O/P)
D3 (FC1 O/P)
D4 (FC2 O/P)
D5
D6 (SCSYNC I/P)
D7 (PALID I/P)
GND
VDD
GND
GND
PXCK
VDD
CLAMP
COMPSYNC
GND
VDD
TDO
TDI
TMS
TCK
GND
SA1
SA2
SCL
VDD
SDA
GND
VDD
PIN
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
FUNCTION
VDD
RESET
REFSQ
GND
VDD
GND
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
GND
VDD
AGND
VREF
DACGAIN
COMP
AVDD
LUMAOUT
AGND
COMPOUT
AGND
CHROMAOUT
AVDD
N/C
N/C
AVDD
AVDD
N/C




VP5311B pdf, 반도체, 판매, 대치품
VP5311B/VP5511B
SDA
SCL
SA1
SA2
I2C INTERFACE
SET-UP
REGISTERS
ANTI-TAPING
CONTROL
CLOSED
CAPTION
CLAMP
RESET
VIDEO TIMING GENERATOR
+
COMPSYNC
INPUT
DEMUX
8
&
PD7-0 CHROMA
INTERP
PXCK
Y
INTERPOLATOR
SYNC
BLANK
INSERT
Cr
CHROMA
LOW -PASS
FILTER
Cb
INT ER POLATOR
MODULATOR
+
LUMA OUT
LUMA
DAC
+ COMP
COMP
DAC
OUT
CHROMA
DAC
CHROMA OUT
8
D7-0
GENERAL
PURPOSE PORT
DIGITAL
PHASE COMP
REFSQ
COLOUR SUBCARRIER
GENERATOR
JTAG.
TDO
TDI
TMS TCK
DAC
REF
DACGAIN
VREF
COMP
Figure 2 Functional block diagram of the VP5311B, the VP5511B is identical except there is no Anti-Taping Control
V
W
H
Peak Glitch Area = H x W/2
The glitch energy is calculated by measuring the area under the voltage
time curve for any LSB step, typically specified in picoVolt-seconds (pV-s)
t(ps)
Figure 3 Glitch Energy
4

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VP5311B 전자부품, 판매, 대치품
REGISTER DETAILS
BAR
RA7-0
Base register
Register address.
PART ID 2-0
ID17-00
Part number
Chip part identification (ID) number.
REV ID
REV7-0
Revision number
Chip revision ID number.
GCR
YCDELAY
Global Control
Luma to Chroma delay.
High = 37ns luma delay, this may be
used to compensate for group delay in
external filters.
Low = normal operation (default).
RAMPEN
SL_HS_VS
CVBSCLMP
Modulated ramp enable.
High = ramp output for differential phase
and gain measurements. A 27MHz clock
must be applied to PXCK pin.
Low = normal operation (default).
1 = Slave to HS and VS inputs
1 = Enables clamp on composite output,
to prevent flatenning of chroma peak
throughs
VFS1-0
VOCR
CLAMPDIS
Video format select
VFS1 VFS0
00
01
10
11
NTSC (default)
PAL-B, D, G,H,I,N(Argentina)
Reserved
Reserved
Video Output Control
High = Clamp signal disable
Low = normal operation with clamp signal
enabled (default).
CHRBW
Chroma bandwidth select.
High = ±1·3MHz.
Low = ±650kHz (default)
SYNCDIS
High = Sync disable (in composite video
signal). COMPSYNC is not affected.
Low = normal operation with sync
enabled (default).
BURDIS
High = Chroma burst disable.
Low = normal operation, with burst
enabled (default).
LUMDIS
High = Luma input disable - force black
level with synchronisation pulses main-
tained.
Low = normal operation, with Luma input
enabled (default).
CHRDIS
High = Chroma input disable - force
monochrome.
Low = normal operation, with Chroma
input enabled (default).
VP5311B/VP5511B
PEDEN
High = Pedestal (set-up) enable a
7·5 IRE pedestal on lines 23-262 and
286-525. Valid for NTSC
HANC
Horizontal Ancillary Data Control
DFI2-0(read only)Digital Field Identification, 000=Field1
ANCTREN
Ancillary timing reference enable. When
High use FIELD COUNT from ancillary
data stream. When low, data is ignored.
ANCID
AN7-1
AN0
Ancillary data ID
Ancillary data ID
Parity bit (odd)
Only ancillary data in REC 656 data
stream with the same ID as this byte will
be decoded by the VP5311/VP5511 to
produce H and V synchronisation and
FIELD COUNT.
SC_ADJ
SC7-0
Sub Carrier Adjust
Sub carrier frequency seed value, see
table 2.
FREQ2-0
FR17-00
Sub carrier frequency
24 bit Sub carrier frequency programmed
via I2C bus, see table 2. FREQ2 is the
most significant byte (MSB).
SCHPHM-L
SCH9-0
Sub carrier phase offset
9 bit Sub carrier phase relative to the
50% point of the leading edge of the
horizontal part of composite sync.
SCHPHM bit 0 is the MSB. The nominal
value is zero. This register is used to
compensate for delays external to the
VP5311/VP5511.
GPPCTL
CTL7-0
General purpose port control
Each bit controls port direction
Low = output High = input
GPPRD
RD7-0
General purpose port read data
I2C bus read from general purpose port
(only INPUTS defined in GPPCTL)
GPPWR
WR7-0
General purpose port write data
I2C bus write to general purpose port
(only OUTPUTS defined in GPPCTL)
CCREG1
F1W1D6-0
Closed Caption register 1
Field one (line 21), first data byte
CCREG2
F1W2D6-0
Closed Caption register 2
Field one (line 21), second data byte
CCREG3
F2W2D6-0
Closed Caption register 3
Field two (line 284), first data byte
CCREG4
F2W2D6-0
Closed Caption register 4
Field two (line 284), second data byte
7

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관련 데이터시트

부품번호상세설명 및 기능제조사
VP5311B

NTSC/PAL Digital Video Encoder

Mitel Networks Corporation
Mitel Networks Corporation
VP5311B

(VP5311B / VP5511B) NTSC/PAL Digital Video Encoder

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