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VP5313 데이터시트 PDF




Mitel Networks Corporation에서 제조한 전자 부품 VP5313은 전자 산업 및 응용 분야에서
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부품번호 VP5313 기능
기능 NTSC/PAL Digital Video Encoder
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VP5313 데이터시트, 핀배열, 회로
VP5313/VP5513
NTSC/PAL Digital Video Encoder
Supersedes DS4509 1.9 September 1997 edition
DS4509 - 2.2 October 1998
The VP5313/VP5513 converts digital Y Cr Cb data into
analog PAL or NTSC composite video, and also provides
33 23
simultaneous RGB outputs. These additional converters can
optionally provide separate luma and chroma outputs plus a
further composite video channel. All outputs are capable of
driving doubly terminated 75loads with standard video
34
22
levels.
All D/A converters are to 9 bit accuracy, and are provided with
27MHz oversampled data. The latter simplifies the
requirement for external analog anti-aliasing filters, and
reduces the sinx/x distortion inherent in D/A converters.
Separate digital scaling is applied to the chroma data path in
order to make the most efficient use of the 9 bit dynamic range.
The device accepts data inputs complying with CCIR
44
12
recommendation 656. In this format 4:2:2 video is multiplexed
onto an 8 bit bus using a 27MHz clock. Active video markers
are embedded into the data stream and extracted by the
VP5313/VP5513. Optionally the user can supply separate
1 11 GP44
horizontal and vertical syncs, and colour can be genlocked to
an external subcarrier if necessary.
In an alternative operating mode the VP5313/VP5513 can
be configured as the source of sync for the rest of the system.
Fig.1 Pin connections (top view)
PIN FUNCTION
1 VDD
PIN FUNCTION
23 SCL
In this master mode the horizontal and vertical sync pins
2
PD5
24 SDA
become outputs, and any control codes in the CCIR656 bit
3
stream are ignored.
4www.DataSheet4U.com
The VP5313/VP5513 supports the insertion of teletext
data through a serial interface. An internal filter shapes the
data edges.
5
6
7
PD6
PD7
CLAMP
COMPSYNC
PALID
25 DACCOMP
26 RED/C
27 GREEN/Y
28 AVDD
29 AGND
FEATURES
s Converts Y, Cr, Cb data to analog RGB and composite
or S-video and composite video
s Supports CCIR recommendations 601 and 656
s All digital video encoding
s Selectable master/slave mode for sync signals
s Switchable chrominance bandwidth
s CCIR 624 PAL SMPTE or 170M NTSC compatible
outputs
s GENLOCK mode
s I2C bus serial microprocessor interface
s Only VP5313 supports Macrovision anti-taping
Rev. 7.01
s Line 21 Closed Caption encoding
s Teletext insertion, fully line programmable
8 SCSYNC
9 REFSQ
10 GND
11 VDD
12 FC2
13 FC1
14 FC0
15 HSYNC
16 VSYNC
17 TTXREQ
18 SA
19 TTXDATA
20 VDD
21 GND
22 RESET
30 AVDD
31 BLUE/CVBS2
32 CVBS1
33 VREF
34 RREF
35 AGND
36 AGND
37 AVDD
38 PD0
39 PD1
40 PD2
41 PD3
42 PD4
43 GND
44 PXCK
APPLICATIONS
s Digital Cable TV
s Digital Satellite TV
s Multi-media
s Video games
s Digital VCRs
s Karaoke
ORDERING INFORMATION
VP5313A/CG/GP1N
VP5513A/CG/GP1N




VP5313 pdf, 반도체, 판매, 대치품
VP5313/VP5513
PIN DESCRIPTIONS
Pin Name
PD0-7
PXCK
Pin No.
2-4,
38-42
44
SA
SCL
SDA
FC0-2
REFSQ
SCSYNC
PALID
COMPSYNC
CLAMP
18
23
24
12-14
9
8
7
6
5
TTXREQ
TTXDATA
HSYNC
VSYNC
RESET
VREF
RREF
17
19
15
16
22
33
34
DACCOMP
CVBS1
25
32
BLUE/CVBS2
GREEN/Y
RED/C
VDD
AVDD
GND
AGND
31
27
26
1, 11, 20
37,28,30
10,21,43
36,29,35
Description
8 Bit Pixel Data inputs clocked by PXCK. PD0 is the least significant bit. These pins are
internally pulled low.
27MHz Pixel Clock input. The VP5313/VP5513 internally divides PXCK by two to provide the
pixel clock.
Slave address select.
Standard I2C bus serial clock input.
Standard I2C bus serial data input/output.
Field Counter output in master sync mode.
Reference square wave input used only during Genlock mode.
Subcarrier sync input, (synchronises phase quadrant in 4xfsc genlock mode), see fig 6.
PAL IDENT input, controls swinging colour burst phase in PAL genlock mode.
Composite sync pulse output. This is an active low output signal.
The CLAMP output signal is synchronised to COMPSYNC output and indicates the position of
the BURST pulse, (lines 10-263 and 273-525 for NTSC; lines 6-310 and 319-623 for PAL-
B,D,G,I,N(Argentina)).
Teletext Data Request output, requests next line of teletext data.
Teletext Data input.
Horizontal Sync, output in master mode, input in slave mode
Vertical Sync, output in master mode, input in slave mode
Master reset. This is an asynchronous, active low, input signal and must be asserted for a
minimum 200ns in order to reset the VP5313/VP5513.
Voltage reference output. This output is nominally 1·0V and should be decoupled with a
100nF capacitor to GND.
DAC full scale current control. A resistor connected between this pin and GND sets the
magnitude of the video output current. An internal loop amplifier controls a reference current
flowing through this resistor so that the voltage across it is equal to the Vref voltage. This
reference current has a weighting equal to 20.8 LSB’s.
DAC compensation. A 100nF ceramic capacitor must be connected to AVDD.
Composite video output. These are high impedance current source outputs. A DC path to
GND must exist from each of these pins.
Blue or composite DAC output. Output type as CVBS1.
Green or luminance DAC output. Output type as CVBS1.
Red or chrominance DAC output. Output type as CVBS1.
Positive supply input. All VDD pins must be connected.
Analog positive supply input. All AVDD pins must be connected.
Negative supply input. All GND pins must be connected.
Analog negative supply input. All AGND pins must be connected.
4

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VP5313 전자부품, 판매, 대치품
REGISTER DETAILS
BAR
RA7-0
Base register
Register address
PART ID 2-0 Part number
ID17-00
Chip part ID number
REV ID
REV7-0
Revision number
Chip revision ID number
MODE
DACCFG
0
1
Mode Control
R,G,B & CVBS analog outputs
Y,C, CVBS1 & CVBS2 analog outputs
VFS1
0
0
1
1
VFS0
0
1
0
1
Video Standard
PAL-B,D,G,H,I,N(Arg.)
NTSC
Reserved
Reserved
SYNCM1 SYNCM0
00
01
10
11
Sync mode
Slave, Rec. 656
Slave H & V I/P
Master H & V O/P
Reserved
GCR
FSC4SEL
0
1
Global Control
Input subcarrier frequency select
REFSQ I/P = Fsubcarrier
SCSYNC I/P ignored
REFSQ I/P = 4 x Fsubcarrier
When SCSYNC I/P is asserted the
REFSQ I/P divide by 4 is reset
GENDITH
0
1
Genlock dither addition control
No dither added
Dither added
GENLKEN
0
1
Genlock enable control
Internal subcarrier generation
When high, enable Genlock to REFSQ
NOLOCK
0
1
Genlock status bit (read only)
Genlocked
Cannot lock to REFSQ.
This bit is cleared by reading and set
again if lock cannot be attained.
PALIDEN
0
1
PAL Ident select
Normal operation, internal PAL switch
is used.
Enables PALID input, a phase control
an for PALID signal, (0 = +135°, 1 = -135°)
VP5313/VP5513
YCDELAY
0
1
Add delay to luma channel
Luma to Chroma delay, 0ns
Luma to Chroma delay, 37ns
CLAMPDIS
0
1
CLAMP O/P select
CLAMP O/P enabled
CLAMP O/P disabled
CVBSCLAMP Composite clamp enable
0 CVBS Clamp disabled
1 Clamps CVBS output, to prevent out of
range DAC codes.
VOCR
DITHEREN
0
1
Video Output Control
Luma dither enable
Normal operation
Luma dither enabled
CHRMCLIP
0
1
Chroma clipping select
No chroma clipping
Enable clipping of chroma data when
luma is clipped
CHRBW
0
1
Chroma bandwidth select
±650kHz
±1·3MHz
SYNCDIS
0
1
Sync disable (in CVBS signal)
Normal operation
Sync disabled
(COMPSYNC O/P is not affected)
BURDIS
0
1
Chroma burst disable
Normal operation
Chroma burst disabled
LUMDIS
0
1
Luma input disable - force black level
Normal operation
Luma disabled
CHRDIS
0
1
Chroma input disable - force monochrome
Normal operation
Chroma disabled
PEDEN
0
1
Pedestal (set-up) select
Valid for NTSC
Pedestal disabled
7·5 IRE pedestal on lines
23-262 and 286-525
7

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