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부품번호 | VPX3225D 기능 |
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기능 | Video Pixel Decoders | ||
제조업체 | ETC | ||
로고 | |||
전체 30 페이지수
MICRONAS
PRELIMINARY DATA SHEET
VPX 3225D,
VPX 3224D
Video Pixel Decoders
Edition Nov. 9, 1998
6251-432-2PD
MICRONAS
VPX 3225D, VPX 3224D
PRELIMINARY DATA SHEET
Contents, continued
Page
Section Title
45 3.
Specifications
45 3.1. Outline Dimensions
48 3.2. Pin Connections and Short Descriptions
45 3.3. Pin Descriptions
47 3.4. Pin Configuration
48 3.5. Pin Circuits
50 4.
Electrical Characteristics
50 4.1. Absolute Maximum Ratings
51 4.2. Recommended Operating Conditions
51
4.2.1.
Recommended Analog Video Input Conditions
52
4.2.2.
Recommended I2C Conditions
52
4.2.3.
Recommended Digital Inputs Levels of RES, OE, TCK, TMS, TDI
53
4.2.4.
Recommended Crystal Characteristics
54 4.3. Characteristics
54
4.3.1.
Current Consumption
54
4.3.2.
Characteristics, Reset
54
4.3.3.
XTAL Input Characteristics
55
4.3.4.
Characteristics, Analog Front-End and ADCs
56
4.3.5.
Characteristics, Control Bus Interface
56
4.3.6.
Characteristics, JTAG Interface (Test Access Port TAP)
57
4.3.7.
Characteristics, Digital Inputs/Outputs
57
4.3.8.
Clock Signals PIXCLK, LLC, and LLC2
58
4.3.9.
Digital Video Interface
58
4.3.10.
Characteristics, TTL Output Driver
59 4.3.10.1. TTL Output Driver Description
60 5.
Timing Diagrams
60 5.1. Power-up Sequence
60 5.2. Default Wake-up Selection
61 5.3. Control Bus Timing Diagram
62 5.4. Output Enable by Pin OE
63 5.5. Timing of the Test Access Port TAP
63 5.6. Timing of all Pins connected to the Boundary-Scan-Register-Chain
64 5.7. Timing Diagram of the Digital Video Interface
64
5.7.1.
Characteristics, Clock Signals
65 6.
Control and Status Registers
65 6.1. Overview
68
6.1.1.
Description of I2C Control and Status Registers
72
6.1.2.
Description of FP Control and Status Registers
4 Micronas
4페이지 PRELIMINARY DATA SHEET
1.1. System Architecture
The block diagram (Fig. 1–1) illustrates the signal flow
through the VPX. A sampling stage performs 8-bit A/D
conversion, clamping, and AGC. The color decoder sep-
arates the luma and chroma signals, demodulates the
chroma, and filters the luminance. A sync slicer detects
the sync edge and computes the skew relative to the
sample clock. The video processing stage resizes the
YCbCr samples, adjusts the contrast and brightness,
and interpolates the chroma. The text slicer extracts
lines with text information and delivers decoded data
bytes to the video interface.
Note: The VPX 3225D and VPX 3224D are not register
compatible with the VPX 3220A, VPX 3216B, and
VPX 3214C family.
VPX 3225D, VPX 3224D
Clock Gen.
DCO
CVBS/Y
ADC
Chroma
SDA
SCL
ADC
I2C JTAG
Sync Processing
Text Slicer
(VPX 3225D only)
Luma Filter
Y
Video Decoder
Chroma
Demodulator
CbCr
Y
CbCr
Line Store
Fig. 1–1: Block diagram of the VPX 3224D, VPX 3225D
Micronas
HREF
VREF
FIELD
A[7:0]
OEQ
B[7:0]
PIXCLK
LLC
VACT
7
7페이지 | |||
구 성 | 총 30 페이지수 | ||
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부품번호 | 상세설명 및 기능 | 제조사 |
VPX3225D | Video Pixel Decoders | ETC |
VPX3225E | Video Pixel Decoders | ETC |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |