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부품번호 | VPX3225E 기능 |
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기능 | Video Pixel Decoders | ||
제조업체 | ETC | ||
로고 | |||
MICRONAS
INTERMETALL
ADVANCE INFORMATION
VPX 3226E,
VPX 3225E,
VPX 3224E
Video Pixel Decoders
Edition Oct. 13, 1999
6251-483-1AI
VPX 322xE
ADVANCE INFORMATION
Contents, continued
Page
Section Title
46 3.
Specifications
46 3.1. Outline Dimensions
47 3.2. Pin Connections and Short Descriptions
49 3.3. Pin Descriptions
50 3.4. Pin Configuration
51 3.5. Pin Circuits
53 4.
Electrical Characteristics
53 4.1. Absolute Maximum Ratings
54 4.2. Recommended Operating Conditions
54
4.2.1.
Recommended Analog Video Input Conditions
55
4.2.2.
Recommended I2C Conditions for Low Power Mode
55
4.2.3.
Recommended Digital Inputs Levels of RES, OE, TCK, TMS, TDI
56
4.2.4.
Recommended Crystal Characteristics
57 4.3. Characteristics
57
4.3.1.
Current Consumption
57
4.3.2.
Characteristics, Reset
57
4.3.3.
XTAL Input Characteristics
58
4.3.4.
Characteristics, Analog Front-End and ADCs
59
4.3.5.
Characteristics, Control Bus Interface
59
4.3.6.
Characteristics, JTAG Interface (Test Access Port TAP)
60
4.3.7.
Characteristics, Digital Inputs/Outputs
60
4.3.8.
Clock Signals PIXCLK, LLC, and LLC2
61
4.3.9.
Digital Video Interface
61
4.3.10.
Characteristics, TTL Output Driver
62 4.3.10.1. TTL Output Driver Description
63 5.
Timing Diagrams
63 5.1. Power-up Sequence
63 5.2. Default Wake-up Selection
64 5.3. Control Bus Timing Diagram
65 5.4. Output Enable by Pin OE
66 5.5. Timing of the Test Access Port TAP
66 5.6. Timing of all Pins connected to the Boundary-Scan-Register-Chain
67 5.7. Timing Diagram of the Digital Video Interface
67
5.7.1.
Characteristics, Clock Signals
68 6.
Control and Status Registers
68 6.1. Overview
71
6.1.1.
Description of I2C Control and Status Registers
75
6.1.2.
Description of FP Control and Status Registers
4 MICRONAS INTERMETALL
4페이지 ADVANCE INFORMATION
1.1. System Architecture
The block diagram (Fig. 1–1) illustrates the signal flow
through the VPX. A sampling stage performs 8-bit A/D
conversion, clamping, and AGC. The color decoder sep-
arates the luma and chroma signals, demodulates the
chroma, and filters the luminance. A sync slicer detects
the sync edge and computes the skew relative to the
sample clock. The video processing stage resizes the
YCbCr samples, adjusts the contrast and brightness,
and interpolates the chroma. The text slicer extracts
lines with text information and delivers decoded data
bytes to the video interface.
Note: The VPX 322xE is register compatible with the
VPX 322xD family, but not with VPX 3220A, VPX 3216B,
and VPX 3214C family.
VPX 322xE
Clock Gen.
DCO
CVBS/Y
ADC
Chroma
SDA
SCL
ADC
I2C JTAG
Sync Processing
Text Slicer
(not VPX 3224E)
Luma Filter
Y
Video Decoder
Chroma
Demodulator
CbCr
Y
CbCr
Line Store
Fig. 1–1: Block diagram of the VPX 322xE
MICRONAS INTERMETALL
HREF
VREF
FIELD
A[7:0]
OEQ
B[7:0]
PIXCLK
LLC
VACT
7
7페이지 | |||
구 성 | 총 30 페이지수 | ||
다운로드 | [ VPX3225E.PDF 데이터시트 ] |
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부품번호 | 상세설명 및 기능 | 제조사 |
VPX3225D | Video Pixel Decoders | ETC |
VPX3225E | Video Pixel Decoders | ETC |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |