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V370PDC 데이터시트 PDF




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부품번호 V370PDC 기능
기능 High Performance PCI SDRAM Controller with Integrated Peripheral Control Unit
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V370PDC 데이터시트, 핀배열, 회로
V370PDC Rev. A0
High Performance PCI SDRAM Controller with
Integrated Peripheral Control Unit
• Fully compliant with PCI 2.2 specification target
interface
• Multiplexed or Non-multiplexed 8-, 16-, or 32-bit
generic peripheral bus interface
• Support up to 1 Gbyte of SDRAM
• Support up to 2 single banks or 1 dual bank
industrial standard 168-pin PC SDRAM DIMM
• Support up to 1Kbyte of burst access from PCI
• Up to 5 programmable chip select for peripheral
strobe generation
• Large On-Chip FIFOs using V3’s unique
DYNAMIC BANDWIDTH ALLOCATION
architecture
Buffered PCI clock output
Hot Swap Ready (PICMGHot Swap
Specification)
Implementation of PCI Bus Power Management
Interface Specification Version 1.0
Initialization through PCI or serial EEPROM
Programmable PCI and local interrupt
management
Two 32-bit General Purpose Timers
Up to 66 MHz local bus clock with asynchronous
PCI clock up to 33MHz
3.3V operation with 5V tolerant inputs
Industrial Temperature Range (-40C to +85C)
Low cost 160-pin PQFP package
The V370PDC PCI SDRAM Controller simplifies the
design of PCI based memory sub-systems. System
designers can replace many lower integration support
components with this single, high-integration device
saving design time, board area, and manufacturing
cost.
The V370PDC from V3 Semiconductor is a high
performance PCI SDRAM Controller with integrated
peripheral control unit operating at up to 66 MHz local
bus speed. It features multiple address translation
units from PCI which allow designers the freedom to
customize their local address space. Access latency of
slower peripherals are absorbed through the large On-
Chip FIFOs.
The peripheral bus provides low latency access to
SDRAM. The peripheral control unit on the V370PDC
also performs address decoding and chip-select
strobes generation for SRAM, PROM and other slow
peripherals. The peripheral bus can also be tri-stated
through a simple hand-shaking protocol to allow other
local bus masters control of the bus.
The SDRAM Controller connects the PCI bus through
on-chip FIFOs to SDRAM arrays of up to 1 Gbytes in
size. The fully programmable SDRAM controller also
supports the use of Enhanced SDRAM to achieve
even greater performance. Burst accesses of up to 1
Kbyte from PCI is supported.
The two general purpose 32-bit timers can be
individually configured as a pulse width modulator, or
used in other modes such as retriggerable or one-
shot. Interrupts for a real time OS can be easily
generated by the system heartbeat timer. A watchdog
timer is also provided for graceful recovery from
catastrophic program failures. Interrupt requests for all
on-chip peripherals are managed by the Interrupt
Control Unit. Additionally, off-chip interrupts can be
routed to the Interrupt Control Unit.
The V370PDC is packaged in a low-cost 160-pin EIJA
Plastic Quad Flat Pack (PQFP), and is available in
66MHz speed grade.
TYPICAL APPLICATION
PCI-to-ISA Conversion
Application
V370PDC
ISA
Conversion
Logic
SDRAM
and PROM
PCI Target Only
Application
V370PDC
SRAM/
FLASH
SDRAM
Copyright © 1999, V3 Semiconductor Corp.
V370PDC_A0 Data Sheet Rev 1.01 DS-PD01-0101
V3 Semiconductor reserves the right to change the specifications of this product without notice.
V370PDC is a trademark of V3 Semiconductor Inc. All other trademarks are the property of their respective owners.
1




V370PDC pdf, 반도체, 판매, 대치품
V370PDC
CAS
MWE
MAD[31:0]
DQM[3:0]
MARB_IN
MARB_OUT
ALE
ADS
BLAST
READY
WNR
SDA
SCL
IOC[11:0]
INT[3:0]
Signal
RSTIN
RSTOUT
CH
Table 3: Signal Descriptions (cont’d)
O12
O12
I/O8
O8
I
O8
O8
O8
O8
I
O8
I/OD
O2
I/O8
I/O8
Type
I
O8
I
Z SDRAM Column Address Strobe
Z SDRAM Memory Write Enable
Z SDRAM and peripheral bus data
Z
SDRAM Data Mask (these act as MBE[3:0], A[1:0] for peripheral
access)
Peripheral bus arbitration input: Treated as bus request input
when V370PDC is the primary bus master. When V370PDC is the
secondary bus master, this input acts as bus grant.
Peripheral bus arbitration output: Treated as bus grant output
0 when V370PDC is the primary bus master. When V370PDC is the
secondary bus master, this output acts bus request.
Z
Address Latch Enable: used to latch the address on MAD[31:0]
during the address phase of a peripheral bus access.
Z Asserted low to indicate the beginning of a bus cycle.
Z Burst last.
Data ready.
Z Write/Read.
Z Serial EEPROM Data
Z Serial EEPROM Clock
Z Multi-purpose I/O that can be configured for many functions
Z
General purpose interrupt inputs/outputs: may be used for either
PCI or local processor interrupts
Mode and Reset
R Description
Reset Input: Active low reset input used to initialize all internal
functions of the chip.
Reset Output: Driven active when the input reset is driven active.
0 Driven inactive when the RSTOUT bit in the system register is set.
The RSTOUT signal is synchronous to the rising edge of CLKIN.
PCI Precharge Bias: This signal is driven low to activate the on-
chip precharge bias for use in PICMG Hot Swap applications.
Non-Hot Swap applications should pull this signal high.
4 V370PDC_A0 Data Sheet Rev 1.01 DS-PD01-0101
Copyright © 1999, V3 Semiconductor Inc.

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V370PDC 전자부품, 판매, 대치품
V370PDC
Figure 1: Pinout for 160-pin EIAJ PQFP (top view)
Copyright © 1999, V3 Semiconductor Corp.
V370PDC_A0 Data Sheet Rev 1.01 DS-PD01-0101
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V370PDC

High Performance PCI SDRAM Controller with Integrated Peripheral Control Unit

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