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V53C16258H 데이터시트 PDF




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부품번호 V53C16258H 기능
기능 HIGH PERFORMANCE 256K X 16 EDO PAGE MODE CMOS DYNAMIC RAM OPTIONAL SELF REFRESH
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V53C16258H 데이터시트, 핀배열, 회로
MOSEL VITELIC
V53C16258H
HIGH PERFORMANCE
256K X 16 EDO PAGE MODE
CMOS DYNAMIC RAM
OPTIONAL SELF REFRESH
PRELIMINARY
HIGH PERFORMANCE
Max. RAS Access Time, (tRAC)
Max. Column Address Access Time, (tCAA)
Min. Extended Data Out Mode Cycle Time, (tPC)
Min. Read/Write Cycle Time, (tRC)
25
25 ns
13 ns
10 ns
45 ns
30
30 ns
16 ns
12 ns
60 ns
35
35 ns
18 ns
14 ns
70 ns
40
40 ns
20 ns
15 ns
75 ns
45
45 ns
22 ns
17 ns
80 ns
50
50 ns
24 ns
19 ns
90 ns
Features
s 256K x 16-bit organization
s EDO Page Mode for a sustained data rate of
100 MHz
s RAS access time: 25, 30, 35, 40, 45, 50 ns
s Dual CAS Inputs
s Low power dissipation
s Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh
s Optional Self Refresh (V53C16258SH)
s Refresh Interval: 512 cycles/8 ms
s Available in 40-pin 400 mil SOJ and 40/44L-pin
400 mil TSOP-II packages
s Single +5V ±10% Power Supply
s TTL Interface
Description
The V53C16258H is a high speed 262,144 x 16
bit high performance CMOS dynamic random
access memory. The V53C16258H offers a
combination of unique features including: EDO
Page Mode operation for higher sustained
bandwidth with Page Mode cycle times as short as
10ns. All inputs are TTL compatible. Input and
output capicatance is significantly lowered to
increase performance and minimize loading. These
features make the V53C16258H ideally suited for a
wide variety of high performance computer systems
and peripheral applications.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
K
T
25 30 35 40 45 50
Std.
Mark
0°C to 70°C
• ••••••
Blank
–40°C to +85°C
• ••••••
I
V53C16258H Rev. 3.8 November 1999
1




V53C16258H pdf, 반도체, 판매, 대치품
MOSEL VITELIC
V53C16258H
DC and Operating Characteristics (1-2)
TA = 0°C to 70°C, VCC = 5 V ± 10%, VSS = 0 V, unless otherwise specified.
Symbol
Parameter
Access
V53C16258H
Time Min. Typ. Max.
Unit
Test Conditions
Notes
ILI Input Leakage Current
(any input pin)
–10 10 µA VSS VIN VCC
ILO Output Leakage Current
(for High-Z State)
ICC1
VCC Supply Current,
Operating
–10
25
30
10 µA VSSVOUT VCC
RAS, CAS at VIH
260 mA tRC = tRC (min.)
200
1, 2
35 190
40 180
45 100
50 90
ICC2
VCC Supply Current,
TTL Standby
ICC3
VCC Supply Current,
RAS-Only Refresh
25
30
2 mA RAS, CAS at VIH
other inputs VSS
260 mA tRC = tRC (min.)
200
2
35 190
40 180
45 100
50 90
ICC4
VCC Supply Current,
25
EDO Page Mode Operation
30
200 mA Minimum Cycle
140
1, 2
35 130
40 120
45 90
50 80
ICC5
VCC Supply Current,
Standby, Output Enabled
other inputs VSS
ICC6
VCC Supply Current,
CMOS Standby
ICC7 Self Refresh Current
VCC Supply Voltage
VIL Input Low Voltage
VIH Input High Voltage
VOL Output Low Voltage
VOH Output High Voltage
2 mA RAS = VIH, CAS = VIL
1
1 mA RAS VCC – 0.2 V,
CAS VCC– 0.2 V,
All other inputs VSS
400 µA CBR Cycle with tRAS tRASS
(Min.) and CAS = VIL;
WE = VCC–0.2V; A0–A8 and
DIN = VCC–0.2V
4.5 5.0 5.5 V
–1 0.8 V
3
2.4 VCC + 1 V
0.4 V IOL = 2 mA
2.4 V IOH = –2 mA
3
V53C16258H Rev. 3.8 November 1999
4

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V53C16258H 전자부품, 판매, 대치품
MOSEL VITELIC
V53C16258H
AC Characteristics (Cont’d)
25
(100 MHz) 30 35 40 45 50
# Symbol Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
54 tOEP
OE High Pulse Width
4 5 8 10 10 10 ns
55 tT
Transition Time (Rise and Fall) 1.5 50 1.5 50 1.5 50 1.5 50 1.5 50 1.5 50 ns
56 tREF
Refresh Interval (512 Cycles)
8 8 8 8 8 8 ms
Optional Self Refresh
15
17
57 tRASS RAS Pulse Width During Self 100 100 100 100 100 100
Refresh
µs 18
58 tRPS
RAS Precharge Time During 100
100
100
100
100
100
Self Refresh
ns 18
59 tCHS
CAS Hold Time Width During 100
100
100
100
100
100
Self Refresh
ns 18
60 tCHD
CAS Low Time During Self
100
100
100
100
100
100
Refresh
µs 18
Notes:
1. ICC is dependent on output loading when the device output is selected. Specified ICC (max.) is measured with the
output open.
2. ICC is dependent upon the number of address transitions. Specified ICC (max.) is measured with a maximum of two
transitions per address cycle in EDO Page Mode.
3. Specified VIL (min.) is steady state operating. During transitions, VIL (min.) may undershoot to –1.0 V for a period
not to exceed 20 ns. All AC parameters are measured with VIL (min.) VSS and VIH (max.) VCC.
4. tRCD (max.) is specified for reference only. Operation within tRCD (max.) limits insures that tRAC (max.) and tCAA
(max.) can be met. If tRCD is greater than the specified tRCD (max.), the access time is controlled by tCAA and tCAC.
5. Either tRRH or tRCH must be satisified for a Read Cycle to occur.
6. Measured with a load equivalent to one TTL input and 50 pF.
7. Access time is determined by the longest of tCAA, tCAC and tCAP.
8. Assumes that tRAD tRAD (max.). If tRAD is greater than tRAD (max.), tRAC will increase by the amount that tRAD
exceeds tRAD (max.).
9. Assumes that tRCD tRCD (max.). If tRCD is greater than tRCD (max.), tRAC will increase by the amount that tRCD
exceeds tRCD (max.).
10. Assumes that tRAD tRAD (max.).
11. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference
point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tCAA and tCAC.
12. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters.
13. tWCS (min.) must be satisfied in an Early Write Cycle.
14. tDS and tDH are referenced to the latter occurrence of CAS or WE.
15. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 3 ns.
16. Assumes a three-state test load (5 pF and a 500 Ohm Thevenin equivalent).
17. An initial 200 µs pause and 8 RAS-containing cycles are required when exiting an extended period of bias without
clocks. An extended period of time without clocks is defined as one that exceeds the specified Refresh Interval.
18. One CBR refresh or complete set of row refreah cycles must be completed upon exiting Self Refreah Mode.
V53C16258H Rev. 3.8 November 1999
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