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V53C808H 데이터시트 PDF




Mosel Vitelic Corp에서 제조한 전자 부품 V53C808H은 전자 산업 및 응용 분야에서
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부품번호 V53C808H 기능
기능 HIGH PERFORMANCE 1M x 8 BIT EDO PAGE MODE CMOS DYNAMIC RAM OPTIONAL SELF REFRESH
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V53C808H 데이터시트, 핀배열, 회로
MOSEL VITELIC
V53C808H
HIGH PERFORMANCE
1M x 8 BIT EDO PAGE MODE
CMOS DYNAMIC RAM
OPTIONAL SELF REFRESH
PRELIMINARY
HIGH PERFORMANCE
Max. RAS Access Time, (tRAC)
Max. Column Address Access Time, (tCAA)
Min. Extended Data Out Mode Cycle Time, (tPC)
Min. Read/Write Cycle Time, (tRC)
Features
s 1M x 8-bit organization
s EDO Page Mode for a sustained data rate
of 72 MHz
s RAS access time: 35, 40, 45, 50 ns
s Low power dissipation
s Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh capability
s Optional Self Refresh (V53C808SH)
s Refresh Interval: 1024 cycles/16 ms
s Available in 28-pin 400 mil SOJ package
s Single +5V ± 10% Power Supply
s TTL Interface
35
35 ns
18 ns
14 ns
70 ns
40
40 ns
20 ns
15 ns
75 ns
45
45 ns
22 ns
17 ns
80 ns
50
50 ns
24 ns
19 ns
90 ns
Description
The V53C808H is a ultra high speed 1,048,576 x
8 bit CMOS dynamic random access memory. The
V53C808H offers a combination of features: Page
Mode with Extended Data Output for high data
bandwidth, and Low CMOS standby current.
All inputs and outputs are TTL compatible. Input
and output capacitances are significantly lowered to
allow increased system performance. Page Mode
with Extended Data Output operation allows ran-
dom access of up to 1024 x 8 bits within a row with
cycle times as fast as 14 ns.
The V53C808H is ideally suited for graphics, dig-
ital signal processing and high-performance com-
puting systems.
Device Usage Chart
Operating
Temperature
Range
0°C to 70 °C
Package Outline
KT
••
Access Time (ns)
35 40 45 50
••••
Power
Std.
Temperature
Mark
Blank
V53C808H Rev. 1.5 April 1998
1




V53C808H pdf, 반도체, 판매, 대치품
MOSEL VITELIC
V53C808H
DC and Operating Characteristics
TA = 0°C to 70°C, VCC = 5 V ± 10%, VSS = 0 V, unless otherwise specified.
Symbol Parameter
Access
Time
V53C808H
Min. Typ. Max.
Unit Test Conditions
Notes
ILI Input Leakage Current
(any input pin)
–10
ILO Output Leakage Current
(for High-Z State)
–10
ICC1
VCC Supply Current,
Operating
35
40
10 mA VSS £ VIN £ VCC
10 mA VSS £ VOUT £ VCC
RAS, CAS at VIH
160 mA tRC = tRC (min.)
150
1, 2
45 145
ICC2
VCC Supply Current,
TTL Standby
ICC3
VCC Supply Current,
RAS-Only Refresh
50
35
40
135
2 mA RAS, CAS at VIH
other inputs ³ VSS
160 mA tRC = tRC (min.)
150
2
45 145
ICC4
VCC Supply Current,
EDO Page Mode
Operation
50
35
40
45
50
135
95 mA Minimum cycle
90
85
80
1, 2
ICC5
VCC Supply Current,
Standby, Output Enabled
ICC6 VCC Supply Current,
CMOS Standby
ICC7 Self Refresh Current
VCC Supply Voltage
VIL Input Low Voltage
VIH Input High Voltage
VOL Output Low Voltage
VOH Output High Voltage
2.0 mA RAS = VIH, CAS = VIL
other inputs ³ VSS
1
2.0 mA RAS ³ VCC – 0.2 V,
CAS ³ VCC– 0.2 V,
All other inputs ³ VSS
400 mA CBR Cycle with tRAS ³ tRASS
(Min.) and CAS = VIL;
WE = VCC–0.2V; A0–A8 and
DIN = VCC–0.2V
4.5 5.0 5.5
V
–1 0.8 V
3
2.4 VCC + 1 V
0.4 V IOL = 2 mA
2.4 V IOH = –2 mA
3
V53C808H Rev. 1.5 April 1998
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V53C808H 전자부품, 판매, 대치품
MOSEL VITELIC
V53C808H
Notes:
1. ICC is dependent on output loading when the device output is selected. Specified ICC (max.) is measured with the
output open.
2. ICC is dependent upon the number of address transitions. Specified IDD (max.) is measured with a maximum of two
transitions per address cycle in EDO Page Mode.
3. Specified VIL (min.) is steady state operating. During transitions, VIL (min.) may undershoot to –1.0 V for a period
not to exceed 20 ns. All AC parameters are measured with VIL (min.) ³ VSS and VIH (max.) £ VDD.
4. tRCD (max.) is specified for reference only. Operation within tRCD (max.) limits insures that tRAC (max.) and tCAA
(max.) can be met. If tRCD is greater than the specified tRCD (max.), the access time is controlled by tCAA and tCAC.
5. Either tRRH or tRCH must be satisified for a Read Cycle to occur.
6. Measured with a load equivalent to one TTL input and 50 pF.
7. Access time is determined by the longest of tCAA, tCAC and tCAP.
8. Assumes that tRAD £ tRAD (max.). If tRAD is greater than tRAD (max.), tRAC will increase by the amount that tRAD ex-
ceeds tRAD (max.).
9. Assumes that tRCD £ tRCD (max.). If tRCD is greater than tRCD (max.), tRAC will increase by the amount that tRCD
exceeds tRCD (max.).
10. Assumes that tRAD ³ tRAD (max.).
11. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference
point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tCAA and tCAC.
12. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters.
13. tWCS (min.) must be satisfied in an Early Write Cycle.
14. tDS and tDH are referenced to the latter occurrence of CAS or WE.
15. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 3 ns.
16. Assumes a three-state test load (5 pF and a 500 Ohm Thevenin equivalent).
17. An initial 200 ms pause and 8 RAS-containing cycles are required when exiting an extended period of bias without
clocks. An extended period of time without clocks is defined as one that exceeds the specified Refresh Interval.
18. Once CBR refresh or complete set of row refresh cycles must be completed upon exiting Self Refresh Mode.
V53C808H Rev. 1.5 April 1998
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