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부품번호 | V53C816H 기능 |
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기능 | 512K X 16 FAST PAGE MODE CMOS DYNAMIC RAM | ||
제조업체 | Mosel Vitelic Corp | ||
로고 | |||
전체 18 페이지수
MOSEL VITELIC
V53C816H
512K X 16 FAST PAGE MODE
CMOS DYNAMIC RAM
PRELIMINARY
HIGH PERFORMANCE
Max. RAS Access Time, (tRAC)
Max. Column Address Access Time, (tCAA)
Min. Fast Page Mode Cycle Time, (tPC)
Min. Read/Write Cycle Time, (tRC)
40
40 ns
20 ns
23 ns
75 ns
45
45 ns
22 ns
25 ns
80 ns
50
50 ns
24 ns
28 ns
90 ns
60
60 ns
30 ns
35 ns
110 ns
Features
s 512K x 16-bit organization
s RAS access time: 40, 45, 50, 60 ns
s Fast Page Mode for a sustained data rate
of 43 MHz
s Dual CAS Inputs
s Pin-to-Pin compatible with 256Kx16
s Low power dissipation
s Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh
s Refresh Interval: 512 cycles/8 ms
s Available in 40-pin 400 mil SOJ
s Single +5V Power Supply
s TTL Interface
Description
The V53C816H is a 524,288 x 16 bit high-perfor-
mance CMOS dynamic random access memory.
The V53C816H offers Fast Page mode with dual
CAS inputs. An address, CAS and RAS input ca-
pacitances are reduced to one half when the
256Kx16 DRAM is used to construct the same
memory density. The V53C816H has asymmetric
address, 10-bit row and 9-bit column.
All inputs are TTL compatible. Fast Page Mode
operation allows random access up to 512K x 16
bits, within a page, with cycle times as short as
23ns.
The V53C816H is best suited for graphics, and
buffer memory applications.
Device Usage Chart
Operating
Temperature
Range
0°C to 70 °C
Package Outline
K
•
Access Time (ns)
40 45 50 60
••••
V53C816H Rev. 1.3 February 1999
1
Power
Std.
•
Temperature
Mark
Blank
MOSEL VITELIC
V53C816H
DC and Operating Characteristics (1-2)
TA = 0°C to 70°C, VCC = 5 V ± 5%, VSS = 0 V, unless otherwise specified.
Symbol
Parameter
Access
V53C816H
Time Min. Typ. Max. Unit
Test Conditions
ILI Input Leakage Current
(any input pin)
–10
ILO Output Leakage Current
(for High-Z State)
–10
ICC1
VCC Supply Current, Operating
40
45
10 µA VSS ≤ VIN ≤ VCC
10 µA VSS≤ VOUT ≤ VCC
RAS, CAS at VIH
220 mA tRC = tRC (min.)
210
50 200
60 190
ICC2
VCC Supply Current,
TTL Standby
ICC3
VCC Supply Current,
RAS-Only Refresh
40
45
4 mA RAS, CAS at VIH
other inputs ≥ VSS
220 mA tRC = tRC (min.)
210
50 200
60 190
ICC4
VCC Supply Current,
Fast Page Mode Operation
40
45
210 mA Minimum Cycle
200
50 190
60 180
ICC5
VCC Supply Current,
Standby, Output Enabled
other inputs ≥ VSS
ICC6
VCC Supply Current,
CMOS Standby
VCC Supply Voltage
VIL Input Low Voltage
VIH Input High Voltage
VOL Output Low Voltage
VOH Output High Voltage
2.0 mA RAS=VIH, CAS=VIL
2.0 mA RAS ≥ VCC – 0.2 V,
CAS ≥ VCC– 0.2 V,
All other inputs ≥ VSS
4.5 5.0 5.5 V
–1 0.8 V
2.4 VCC+1 V
0.4 V IOL = 2.0 mA
2.4 V IOH = –2.0 mA
Notes
1, 2
2
1, 2
1
3
3
V53C816H Rev. 1.3 February 1999
4
4페이지 MOSEL VITELIC
V53C816H
Notes:
1. ICC is dependent on output loading when the device output is selected. Specified ICC (max.) is
measured with the output open.
2. ICC is dependent upon the number of address transitions. Specified ICC (max.) is measured with a
maximum of two transitions per address cycle in Fast Page Mode.
3. Specified VIL (min.) is steady state operating. During transitions, VIL (min.) may undershoot to –1.0 V for a period
not to exceed 20 ns. All AC parameters are measured with VIL (min.) ≥ VSS and VIH (max.) ≤ VCC.
4. tRCD (max.) is specified for reference only. Operation within tRCD (max.) limits insures that tRAC (max.) and tCAA
(max.) can be met. If tRCD is greater than the specified tRCD (max.), the access time is controlled by tCAA and tCAC.
5. Either tRRH or tRCH must be satisified for a Read Cycle to occur.
6. Measured with a load equivalent to one TTL input and 50 pF.
7. Access time is determined by the longest of tCAA, tCAC and tCAP.
8. Assumes that tRAD ≤ tRAD (max.). If tRAD is greater than tRAD (max.), tRAC will increase by the amount that tRAD
exceeds tRAD (max.).
9. Assumes that tRCD ≤ tRCD (max.). If tRCD is greater than tRCD (max.), tRAC will increase by the amount that tRCD
exceeds tRCD (max.).
10. Assumes that tRAD ≥ tRAD (max.).
11. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference
point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tCAA and tCAC.
12. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters.
13. tWCS (min.) must be satisfied in an Early Write Cycle.
14. tDS and tDH are referenced to the latter occurrence of CAS or WE.
15. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 3 ns.
16. Assumes a three-state test load (5 pF and a 380 Ohm Thevenin equivalent).
17. An initial 200 µs pause and 8 RAS-containing cycles are required when exiting an extended period of bias without
clocks. An extended period of time without clocks is defined as one that exceeds the specified Refresh Interval.
V53C816H Rev. 1.3 February 1999
7
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부품번호 | 상세설명 및 기능 | 제조사 |
V53C816H | 512K X 16 FAST PAGE MODE CMOS DYNAMIC RAM | Mosel Vitelic Corp |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |