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PDF V54C3128404VBGA Data sheet ( Hoja de datos )
| Número de pieza | V54C3128404VBGA | |
| Descripción | 128Mbit SDRAM 3.3 VOLT/ BGA PACKAGE | |
| Fabricantes | Mosel Vitelic Corp | |
| Logotipo |  |
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MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
128Mbit SDRAM
3.3 VOLT, BGA PACKAGE
8M X 16
16M X 8
32M X 4
System Frequency (fCK)
Clock Cycle Time (tCK3)
Clock Access Time (tAC3) CAS Latency = 3
Clock Access Time (tAC2) CAS Latency = 2
6
166 MHz
6 ns
5.4 ns
5.4 ns
7PC
143 MHz
7 ns
5.4 ns
5.4 ns
PRELIMINARY
7
143 MHz
7 ns
5.4 ns
6 ns
8PC
125 MHz
8 ns
6 ns
6 ns
Features
s 4 banks x 2Mbit x 16 organization
s 4 banks x 4Mbit x 8 organization
s 4 banks x 8Mbit x 4 organization
s High speed data transfer rates up to 166 MHz
s Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
s Single Pulsed RAS Interface
s Data Mask for Read/Write Control
s Four Banks controlled by BA0 & BA1
s Programmable CAS Latency: 2, 3
s Programmable Wrap Sequence: Sequential or
Interleave
s Programmable Burst Length:
1, 2, 4, 8 for Sequential Type
1, 2, 4, 8 for Interleave Type
s Multiple Burst Read with Single Write Operation
s Automatic and Controlled Precharge Command
s Random Column Address every CLK (1-N Rule)
s Power Down Mode
s Auto Refresh and Self Refresh
s Refresh Interval: 4096 cycles/64 ms
s Available in 60 Pin WBGA
s LVTTL Interface
s Single +3.3 V ±0.3 V Power Supply
Description
The V54C3128(16/80/40)4V(BGA) is a four bank
Synchronous DRAM organized as 4 banks x 2Mbit
x 16, 4 banks x 4Mbit x 8, or 4 banks x 8Mbit x 4.
The V54C3128(16/80/40)4V(BGA) achieves high
speed data transfer rates up to 166 MHz by employ-
ing a chip architecture that prefetches multiple bits
and then synchronizes the output data to a system
clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
166 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
B
•
6
•
Access Time (ns)
7PC 7
••
8PC
•
Power
Std. L
••
Temperature
Mark
Blank
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
1
1 page  
MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
Block Diagram
x4 Configuration
Column Addresses
A0 - A9, A11, AP, BA0, BA1
Row Addresses
A0 - A11, BA0, BA1
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Bank 0
4096 x 2048
x 4 bit
Row decoder
Memory array
Bank 1
4096 x 2048
x 4 bit
Row decoder
Memory array
Bank 2
4096 x 2048
x 4 bit
Row decoder
Memory array
Bank 3
4096 x 2048
x 4 bit
Input buffer Output buffer
I/O1-I/O4
Control logic & timing generator
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
5
5 Page 
MOSEL VITELIC
with Auto-Precharge function is initiated. The
SDRAM automatically enters the precharge opera-
tion a time delay equal to tWR (Write recovery time)
after the last data in.
Precharge Command
There is also a separate precharge command
available. When RAS and WE are low and CAS is
high at a clock timing, it triggers the precharge
operation. Three address bits, BA0, BA1 and A10
are used to define banks as shown in the following
list. The precharge command can be imposed one
clock before the last data out for CAS latency = 2,
two clocks before the last data out for CAS latency
= 3. Writes require a time delay twr from the last
data out to apply the precharge command.
Bank Selection by Address Bits:
A10 BA0 BA1
000
001
010
011
1XX
Bank 0
Bank 1
Bank 2
Bank 3
all Banks
V54C3128(16/80/40)4V(BGA)
Burst Termination
Once a burst read or write operation has been ini-
tiated, there are several methods in which to termi-
nate the burst operation prematurely. These
methods include using another Read or Write Com-
mand to interrupt an existing burst operation, use a
Precharge Command to interrupt a burst cycle and
close the active bank, or using the Burst Stop Com-
mand to terminate the existing burst operation but
leave the bank open for future Read or Write Com-
mands to the same page of the active bank. When
interrupting a burst with another Read or Write
Command care must be taken to avoid I/O conten-
tion. The Burst Stop Command, however, has the
fewest restrictions making it the easiest method to
use when terminating a burst operation before it has
been completed. If a Burst Stop command is issued
during a burst write operation, then any residual
data from the burst write cycle will be ignored. Data
that is presented on the I/O pins before the Burst
Stop Command is registered will be written to the
memory.
Recommended Operation and Characteristics for LV-TTL
TA = 0 to 70 °C; VSS = 0 V; VCC,VCCQ = 3.3 V ± 0.3 V
Limit Values
Parameter
Symbol
min.
max. Unit Notes
Input high voltage
VIH 2.0 Vcc+0.3 V 1, 2
Input low voltage
VIL – 0.3
0.8 V 1, 2
Output high voltage (IOUT = – 4.0 mA)
VOH
2.4
–V
Output low voltage (IOUT = 4.0 mA)
VOL –
0.4 V
Input leakage current, any input
(0 V < VIN < 3.6 V, all other inputs = 0 V)
II(L) – 5
5 µA
Output leakage current
(DQ is disabled, 0 V < VOUT < VCC)
IO(L)
–5
5 µA
Note:
1. All voltages are referenced to VSS.
2. VIH may overshoot to VCC + 2.0 V for pulse width of < 4ns with 3.3V. VIL may undershoot to -2.0 V for pulse width < 4.0 ns with
3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference.
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
11
11 Page | ||
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