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V54C3128804VBGA 데이터시트 PDF




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부품번호 V54C3128804VBGA 기능
기능 128Mbit SDRAM 3.3 VOLT/ BGA PACKAGE
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V54C3128804VBGA 데이터시트, 핀배열, 회로
MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
128Mbit SDRAM
3.3 VOLT, BGA PACKAGE
8M X 16
16M X 8
32M X 4
System Frequency (fCK)
Clock Cycle Time (tCK3)
Clock Access Time (tAC3) CAS Latency = 3
Clock Access Time (tAC2) CAS Latency = 2
6
166 MHz
6 ns
5.4 ns
5.4 ns
7PC
143 MHz
7 ns
5.4 ns
5.4 ns
PRELIMINARY
7
143 MHz
7 ns
5.4 ns
6 ns
8PC
125 MHz
8 ns
6 ns
6 ns
Features
s 4 banks x 2Mbit x 16 organization
s 4 banks x 4Mbit x 8 organization
s 4 banks x 8Mbit x 4 organization
s High speed data transfer rates up to 166 MHz
s Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
s Single Pulsed RAS Interface
s Data Mask for Read/Write Control
s Four Banks controlled by BA0 & BA1
s Programmable CAS Latency: 2, 3
s Programmable Wrap Sequence: Sequential or
Interleave
s Programmable Burst Length:
1, 2, 4, 8 for Sequential Type
1, 2, 4, 8 for Interleave Type
s Multiple Burst Read with Single Write Operation
s Automatic and Controlled Precharge Command
s Random Column Address every CLK (1-N Rule)
s Power Down Mode
s Auto Refresh and Self Refresh
s Refresh Interval: 4096 cycles/64 ms
s Available in 60 Pin WBGA
s LVTTL Interface
s Single +3.3 V ±0.3 V Power Supply
Description
The V54C3128(16/80/40)4V(BGA) is a four bank
Synchronous DRAM organized as 4 banks x 2Mbit
x 16, 4 banks x 4Mbit x 8, or 4 banks x 8Mbit x 4.
The V54C3128(16/80/40)4V(BGA) achieves high
speed data transfer rates up to 166 MHz by employ-
ing a chip architecture that prefetches multiple bits
and then synchronizes the output data to a system
clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
166 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
B
6
Access Time (ns)
7PC 7
••
8PC
Power
Std. L
••
Temperature
Mark
Blank
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
1




V54C3128804VBGA pdf, 반도체, 판매, 대치품
MOSEL VITELIC
Block Diagram
V54C3128(16/80/40)4V(BGA)
x8 Configuration
Column Addresses
A0 - A9, AP, BA0, BA1
Row Addresses
A0 - A11, BA0, BA1
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Bank 0
4096 x 1024
x 8 bit
Row decoder
Memory array
Bank 1
4096 x 1024
x 8 bit
Row decoder
Memory array
Bank 2
4096 x 1024
x 8 bit
Row decoder
Memory array
Bank 3
4096 x 1024
x 8 bit
Input buffer Output buffer
I/O1-I/O8
Control logic & timing generator
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
4

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V54C3128804VBGA 전자부품, 판매, 대치품
MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the
positive edge of the clock. The following list shows the thruth table for the operation commands.
Operation
Row Activate
Read
Read w/Autoprecharge
Write
Write with Autoprecharge
Row Precharge
Precharge All
Mode Register Set
No Operation
Device Deselect
Auto Refresh
Self Refresh Entry
Self Refresh Exit
Power Down Entry
Power Down Exit
Data Write/Output Enable
Data Write/Output Disable
Device CKE CKE
A0-9,
BS0
State n-1 n CS RAS CAS WE DQM A11 A10 BS1
Idle3 H X L L H H X V V V
Active3
H
X
LHLHXVL
V
Active3
H
X
L
H
L
H
X
V
H
V
Active3
H
X
LHL
L
XVL
V
Active3
H
X
L
H
L
L
X
V
H
V
Any H X L L H L X X L V
Any H X L L H L X X H X
Idle H X L L L L X V V V
Any
HX
L HHH X
XX
X
Any H X H X X X X X X X
Idle H H L L L H X X X X
Idle H L L L L H X X X X
Idle H X X X
(Self Refr.) L
H
XXX X
LHHX
Idle H X X X
Active4
H
L
XXX X
LHHX
Any H X X X
(Power
L
H
XXX X
Down)
LHHL
Active H X X X X X L X X X
Active H X X X X X H X X X
Notes:
1. V = Valid , x = Dont Care, L = Low Level, H = High Level
2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands
are provided.
3. These are state of bank designated by BS0, BS1 signals.
4. Power Down Mode can not entry in the burst cycle.
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
7

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V54C3128804VBGA

128Mbit SDRAM 3.3 VOLT/ BGA PACKAGE

Mosel Vitelic  Corp
Mosel Vitelic Corp

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