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V54C316162 데이터시트 PDF




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부품번호 V54C316162 기능
기능 200/183/166/143 MHz 3.3 VOLT/ 4K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16
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V54C316162 데이터시트, 핀배열, 회로
MOSEL VITELIC
V54C316162V
200/183/166/143 MHz 3.3 VOLT, 4K REFRESH
ULTRA HIGH PERFORMANCE
1M X 16 SDRAM 2 BANKS X 512Kbit X 16
V54C316162V
Clock Frequency (tCK)
Latency
Cycle Time (tCK)
Access Time (tAC)
-5 -55 -6
-7 Unit
200 183 166 143 MHz
3 3 3 3 clocks
5 5.5 6
7 ns
5 5.3 5.5 5.5 ns
Features
s JEDEC Standard 3.3V Power Supply
s The V54C316162V is ideally suited for high per-
formance graphics peripheral applications
s Single Pulsed RAS Interface
s Programmable CAS Latency: 2, 3
s All Inputs are sampled at the positive going edge
of clock
s Programmable Wrap Sequence: Sequential or
Interleave
s Programmable Burst Length: 1, 2, 4, 8 and Full
Page for Sequential and 1, 2, 4, 8 for Interleave
s UDQM & LDQM for byte masking
s Auto & Self Refresh
s 4K Refresh Cycles/64 ms
s Burst Read with Single Write Operation
Description
The V54C316162V is a 16,777,216 bits synchro-
nous high data rate DRAM organized as 2 x
524,288 words by 16 bits. The device is designed to
comply with JEDEC standards set for synchronous
DRAM products, both electrically and mechanically.
Synchronous design allows precise cycle control
with the system clock. The CAS latency, burst
length and burst sequence must be programmed
into device prior to access operation.
V54C316162V Rev.2.9 September 2001
1




V54C316162 pdf, 반도체, 판매, 대치품
MOSEL VITELIC
Signal Pin Description
Pin
CLK
CKE
Name
Clock Input
Clock Enable
CS
RAS
CAS
WE
A0-A10
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address
BA Bank Select
I/O1-I/O16
UDQM, LDQM
Data Input/Output
Data Input/Output Mask
VDD/VSS
Power Supply/Ground
VDDQ/VSSQ Data Output Power/Ground
NC No Connection
V54C316162V
Input Function
System clock input. Active on the positive rising edge to sample all inptus
Activates the CLK signal when high and deactivates the CLK when low.
CKE low initiates the power down mode, suspend mode, or the self
refresh mode
Disables or enables device operation by masking or enabling all inputs
except CLK, CKE and DQMi
Latches row addresses on the positive edge of CLK with RAS low.
Enables row access & precharge
Latches column addresses on the positive edge of CLK with CAS low.
Enables column access
Enables write operation
During a bank activate command, A0-A10 defines the row address.
During a read or write command, A0-A7 defines the column address. In
addition to the column address A10 is used to invoke auto precharge BA
define the bank to be precharged. A10 is low, auto precharge is disabled
during a precharge cycle, If A10 is high, both bank will be precharged ,
if A10 is low, the BA is used to decide which bank to precharge. If A10 is
high, all banks will be precharged.
Selects which bank to activate. BA low select bank A and high selects
bank B
Data inputs/output are multiplexed on the same pins
Makes data output Hi-Z. Blocks data input when DQM is active
Power Supply. +3.3V ± 0.3V/ground
Provides isolated power/ground to DQs for improved noise immunity
V54C316162V Rev.2.9 September 2001
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V54C316162 전자부품, 판매, 대치품
MOSEL VITELIC
The chip enters the Auto Refresh mode, when
RAS and CAS are held low and CKE and WE are
held high at a clock timing. The mode restores word
line after the refresh and no external precharge
command is necessary. A minimum tRC time is re-
quired between two automatic refreshes in a burst
refresh mode. The same rule applies to any access
command after the automatic refresh operation.
The chip has an on-chip timer and the Self Re-
fresh mode is available. It enters the mode when
RAS, CAS, and CKE are low and WE is high at a
clock timing. All of external control signals including
the clock are disabled. Returning CKE to high en-
ables the clock and initiates the refresh exit opera-
tion. After the exit command, at least one tRC delay
is required prior to any access command.
DQM Function
DQM has two functions for data I/O read and
write operations. During reads, when it turns to
highat a clock timing, data outputs are disabled
and become high impedance after two clock delay
(DQM Data Disable Latency tDQZ ). It also provides
a data mask function for writes. When DQM is acti-
vated, the write operation at the next clock is prohib-
ited (DQM Write Mask Latency tDQW = zero clocks).
DQM is used for device selection, byte selection
and bus control in a memory system. LDQM con-
trols DQ0 to DQ7, UDQM controls DQ8 to DQ15.
Suspend Mode
During normal access mode, CKE is held high en-
abling the clock. When CKE is low, it freezes the in-
ternal clock and extends data read and write
operations. One clock delay is required for mode
entry and exit (Clock Suspend Latency tCSL).
Power Down
In order to reduce standby power consumption, a
power down mode is available. All banks must be
precharged and the necessary Precharge delay
(trp) must occur before the SDRAM can enter the
Power Down mode. Once the Power Down mode is
initiated by holding CKE low, all of the receiver cir-
cuits except CLK and CKE are gated off. The Power
Down mode does not perform any refresh opera-
tions, therefore the device cant remain in Power
Down mode longer than the Refresh period (tref) of
the device. Exit from this mode is performed by tak-
ing CKE high. One clock delay is required for
mode entry and exit.
V54C316162V
Auto Precharge
Two methods are available to precharge
SDRAMs. In an automatic precharge mode, the
CAS timing accepts one extra address, A10, to de-
termine whether the chip restores or not after the
operation. If A10 is high when a Read Command is
issued, the Read with Auto-Precharge function is
initiated. The SDRAM automatically enters the pre-
charge operation one clock before the last data out
for CAS latencies 2, two clocks for CAS latencies 3.
If A10 is high when a Write Command is issued, the
Write with Auto-Precharge function is initiated.
The SDRAM automatically enters the precharge op-
eration a time delay equal to tWR (Write recovery
time) after the last data in.
Precharge Command
There is also a separate precharge command
available. When RAS and WE are low and CAS is
high at a clock timing, it triggers the precharge op-
eration. With A10 being low, the BA is used select
bank to precharge. The precharge command can be
imposed one clock before the last data out for CAS
latency = 2, two clocks before the last data out for
CAS latency = 3. Writes require a time delay twr
from the last data out to apply the precharge com-
mand. If A10 is high, all banks will be precharged.
Burst Termination
Once a burst read or write operation has been ini-
tiated, there are several methods in which to termi-
nate the burst operation prematurely. These
methods include using another Read or Write Com-
mand to interrupt an existing burst operation, use a
Precharge Command to interrupt a burst cycle and
close the active bank, or using the Burst Stop Com-
mand to terminate the existing burst operation but
leave the bank open for future Read or Write Com-
mands to the same page of the active bank. When
interrupting a burst with another Read or Write
Command care must be taken to avoid I/O conten-
tion. The Burst Stop Command, however, has the
fewest restrictions making it the easiest method to
use when terminating a burst operation before it has
been completed. If a Burst Stop command is issued
during a burst write operation, then any residual
data from the burst write cycle will be ignored. Data
that is presented on the I/O pins before the Burst
Stop Command is registered will be written to the
memory.
V54C316162V Rev. 2.9 September 2001
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부품번호상세설명 및 기능제조사
V54C316162

200/183/166/143 MHz 3.3 VOLT/ 4K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16

Mosel Vitelic  Corp
Mosel Vitelic Corp
V54C316164VE

(V54C3xxxx4VE) 64Mbit SDRAM

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