Datasheet.kr   

V54C3256164VBUT 데이터시트 PDF




Mosel Vitelic Corp에서 제조한 전자 부품 V54C3256164VBUT은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 V54C3256164VBUT 자료 제공

부품번호 V54C3256164VBUT 기능
기능 LOW POWER 256Mbit SDRAM 3.3 VOLT/ 54-BALL SOC BGA 54-PIN TSOPII 16M X 16
제조업체 Mosel Vitelic Corp
로고 Mosel Vitelic  Corp 로고


V54C3256164VBUT 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.



전체 30 페이지수

미리보기를 사용할 수 없습니다

V54C3256164VBUT 데이터시트, 핀배열, 회로
MOSEL VITELIC
V54C3256164VBUC/T
LOW POWER 256Mbit SDRAM
3.3 VOLT, 54-BALL SOC BGA
54-PIN TSOPII 16M X 16
PRELIMINARY
System Frequency (fCK)
Clock Cycle Time (tCK3)
Clock Access Time (tAC3) CAS Latency = 3
Clock Access Time (tAC2) CAS Latency = 2
6
166 MHz
6 ns
5.4 ns
5.4 ns
7PC
143 MHz
7 ns
5.4 ns
5.4 ns
7
143 MHz
7 ns
5.4 ns
6 ns
8PC
125 MHz
8 ns
6 ns
6 ns
Features
4 banks x 4Mbit x 16 organization
High speed data transfer rates up to 166 MHz
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
Single Pulsed RAS Interface
Data Mask for Read/Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 3
Programmable Wrap Sequence: Sequential or
Interleave
Programmable Burst Length:
1, 2, 4, 8 for Sequential Type
1, 2, 4, 8 for Interleave Type
Multiple Burst Read with Single Write Operation
Automatic and Controlled Precharge Command
Random Column Address every CLK (1-N Rule)
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 8192 cycles/64 ms
Available in 54-Ball SOC BGA/ 54-Pin TSOP II
LVTTL Interface
Single +3.3 V ±0.3 V Power Supply
Low Power Self Refresh Current
L-version 1.0mA
U-version 0.6mA
Description
The V54C3256164VBUC/T is a low power four
bank Synchronous DRAM organized as 4 banks x
4Mbit x 16. The V54C3256164VBUC/T achieves
high speed data transfer rates up to 166 MHz by
employing a chip architecture that prefetches multi-
ple bits and then synchronizes the output data to a
system clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
166 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
The V54C3256164VBUC/T is ideally suited for
high performance, low power systems such as
PDA, mobile phone, DSC, and other battery backup
applications.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Out-
line
C/T
Access Time (ns)
6 7PC 7 8PC
••••
Std.
Power
LU
••
Temperature
T Mark
• Blank
V54C3256164VBUC/T Rev. 1.1 February 2003
1




V54C3256164VBUT pdf, 반도체, 판매, 대치품
MOSEL VITELIC
Capacitance*
TA = 0 to 70°C, VCC = 3.3 V ± 0.3 V, f = 1 Mhz
Symbol Parameter
Max. Unit
CI1 Input Capacitance (A0 to A12)
5 pF
CI2 Input Capacitance
5 pF
RAS, CAS, WE, CS, CLK, CKE, DQM
CIO
CCLK
Output Capacitance (I/O)
Input Capacitance (CLK)
6.5 pF
4 pF
*Note:Capacitance is sampled and not 100% tested.
V54C3256164VBUC/T
Absolute Maximum Ratings*
Operating temperature range .................. 0 to 70 °C
Storage temperature range ................-55 to 150 °C
Input/output voltage.................. -0.3 to (VCC+0.3) V
Power supply voltage .......................... -0.3 to 4.6 V
Power dissipation ..............................................1 W
Data out current (short circuit).......................50 mA
*Note:
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage of the device.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Block Diagram
x16 Configuration
Column Addresses
A0 - A8, AP, BA0, BA1
Row Addresses
A0 - A12, BA0, BA1
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Bank 0
8192 x 512
x 16 bit
Row decoder
Memory array
Bank 1
8192 x 512
x16 bit
Row decoder
Memory array
Bank 2
8192 x 512
x 16 bit
Row decoder
Memory array
Bank 3
8192 x 512
x 16 bit
Input buffer Output buffer
I/O1-I/O16
Control logic & timing generator
V54C3256164VBUC/T Rev1.1 February 2003
4

4페이지










V54C3256164VBUT 전자부품, 판매, 대치품
MOSEL VITELIC
Power On and Initialization
The default power on state of the mode register is
supplier specific and may be undefined. The
following power on and initialization sequence
guarantees the device is preconditioned to each
users specific needs. Like a conventional DRAM,
the Synchronous DRAM must be powered up and
initialized in a predefined manner. During power on,
all VCC and VCCQ pins must be built up
simultaneously to the specified voltage when the
input signals are held in the “NOP” state. The power
on voltage must not exceed VCC+0.3V on any of
the input pins or VCC supplies. The CLK signal
must be started at the same time. After power on,
an initial pause of 200 µs is required followed by a
precharge of both banks using the precharge
command. To prevent data contention on the DQ
bus during power on, it is required that the DQM and
CKE pins be held high during the initial pause
period. Once all banks have been precharged, the
Mode Register Set Command must be issued to
initialize the Mode Register. A minimum of eight
Auto Refresh cycles (CBR) are also required.These
may be done before or after programming the Mode
Register. Failure to follow these steps may lead to
unpredictable start-up modes.
Programming the Mode Register
The Mode register designates the operation
mode at the read or write cycle. This register is di-
vided into 4 fields. A Burst Length Field to set the
length of the burst, an Addressing Selection bit to
program the column access sequence in a burst cy-
cle (interleaved or sequential), a CAS Latency Field
to set the access time at clock cycle and a Opera-
tion mode field to differentiate between normal op-
eration (Burst read and burst Write) and a special
Burst Read and Single Write mode. The mode set
V54C3256164VBUC/T
operation must be done before any activate com-
mand after the initial power up. Any content of the
mode register can be altered by re-executing the
mode set command. All banks must be in pre-
charged state and CKE must be high at least one
clock before the mode set operation. After the mode
register is set, a Standby or NOP command is re-
quired. Low signals of RAS, CAS, and WE at the
positive edge of the clock activate the mode set op-
eration. Address input data at this timing defines pa-
rameters to be set as shown in the previous table.
Read and Write Operation
When RAS is low and both CAS and WE are high
at the positive edge of the clock, a RAS cycle starts.
According to address data, a word line of the select-
ed bank is activated and all of sense amplifiers as-
sociated to the wordline are set. A CAS cycle is
triggered by setting RAS high and CAS low at a
clock timing after a necessary delay, tRCD, from the
RAS timing. WE is used to define either a read
(WE = H) or a write (WE = L) at this stage.
SDRAM provides a wide variety of fast access
modes. In a single CAS cycle, serial data read or
write operations are allowed at up to a 125 MHz
data rate. The numbers of serial data bits are the
burst length programmed at the mode set operation,
i.e., one of 1, 2, 4, 8. Column addresses are seg-
mented by the burst length and serial data accesses
are done within this boundary. The first column ad-
dress to be accessed is supplied at the CAS timing
and the subsequent addresses are generated auto-
matically by the programmed burst length and its
sequence. For example, in a burst length of 8 with
interleave sequence, if the first address is ‘2’, then
the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and
5.
V54C3256164VBUC/T Rev. 1.1 February 2003
7

7페이지


구       성 총 30 페이지수
다운로드[ V54C3256164VBUT.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
V54C3256164VBUC

LOW POWER 256Mbit SDRAM 3.3 VOLT/ 54-BALL SOC BGA 54-PIN TSOPII 16M X 16

Mosel Vitelic  Corp
Mosel Vitelic Corp
V54C3256164VBUT

LOW POWER 256Mbit SDRAM 3.3 VOLT/ 54-BALL SOC BGA 54-PIN TSOPII 16M X 16

Mosel Vitelic  Corp
Mosel Vitelic Corp

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵