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V54C3256804VB 데이터시트 PDF




Mosel Vitelic Corp에서 제조한 전자 부품 V54C3256804VB은 전자 산업 및 응용 분야에서
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부품번호 V54C3256804VB 기능
기능 256Mbit SDRAM 3.3 VOLT/ TSOP II / SOC BGA / WBGA PACKAGE 16M X 16/ 32M X 8/ 64M X 4
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V54C3256804VB 데이터시트, 핀배열, 회로
MOSEL VITELIC
V54C3256(16/80/40)4V(T/S/B)
256Mbit SDRAM
3.3 VOLT, TSOP II / SOC BGA / WBGA
PACKAGE 16M X 16, 32M X 8, 64M X 4
PRELIMINARY
System Frequency (fCK)
Clock Cycle Time (tCK3)
Clock Access Time (tAC3) CAS Latency = 3
Clock Access Time (tAC2) CAS Latency = 2
6
166 MHz
6 ns
5.4 ns
5.4 ns
7PC
143 MHz
7 ns
5.4 ns
5.4 ns
7
143 MHz
7 ns
5.4 ns
6 ns
8PC
125 MHz
8 ns
6 ns
6 ns
Features
4 banks x 4Mbit x 16 organization
4 banks x 8Mbit x 8 organization
4 banks x16Mbit x 4 organization
High speed data transfer rates up to 166 MHz
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
Single Pulsed RAS Interface
Data Mask for Read/Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 3
Programmable Wrap Sequence: Sequential or
Interleave
Programmable Burst Length:
1, 2, 4, 8 for Sequential Type
1, 2, 4, 8 for Interleave Type
Multiple Burst Read with Single Write Operation
Automatic and Controlled Precharge Command
Random Column Address every CLK (1-N Rule)
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 8192 cycles/64 ms
Available in 54 Pin TSOP II, 60 Ball WBGA and
SOC BGA
LVTTL Interface
Single +3.3 V ±0.3 V Power Supply
Description
The V54C3256(16/80/40)4V(T/S/B) is a four
bank Synchronous DRAM organized as 4 banks x
4Mbit x 16, 4 banks x 8Mbit x 8, or 4 banks x 16Mbit
x 4. The V54C3256(16/80/40)4V(T/S/B) achieves
high speed data transfer rates up to 166 MHz by
employing a chip architecture that prefetches multi-
ple bits and then synchronizes the output data to a
system clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
166 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
T/S/B
6
Access Time (ns)
7PC 7
••
8PC
Power
Std. L
••
Temperature
Mark
Blank
V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002
1




V54C3256804VB pdf, 반도체, 판매, 대치품
MOSEL VITELIC
V54C3256(16/80/40)4V(T/S/B)
Description Pkg.
TSOP-II
T
Pin Count
54
V 54 C 3 25680 4 V A L T
Mosel Vitelic
Manufactured
SYNCHRONOUS
DRAM FAMILY
Device
Number
C=CMOS Family
3.3V, LVTTL INTERFACE
32Mx8(8K Refresh)
4 Banks
Special
Feature
Speed
6 ns
7 ns
8 ns
TSOP Component
Package
L=Low Power
Component Rev Level A=0.17um
V=LVTTL
B=0.14um
54 Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
VCC
I/O1
VCCQ
NC
I/O2
VSSQ
NC
I/O3
VCCQ
NC
I/O4
VSSQ
NC
VCC
NC
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
356804V-01
VSS
I/O8
VSSQ
NC
I/O7
VCCQ
NC
I/O6
VSSQ
NC
I/O5
VCCQ
NC
VSS
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
Pin Names
CLK
CKE
CS
RAS
CAS
WE
A0–A12
BA0, BA1
I/O1–I/O8
DQM
VCC
VSS
VCCQ
VSSQ
NC
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address Inputs
Bank Select
Data Input/Output
Data Mask
Power (+3.3V)
Ground
Power for I/O’s (+3.3V)
Ground for I/O’s
Not connected
V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002
4

4페이지










V54C3256804VB 전자부품, 판매, 대치품
MOSEL VITELIC
V54C3256(16/80/40)4V(T/S/B)
Description Pkg.
WBGA
B
V 54 C 3 256XX 4 V A L B
Mosel Vitelic
Manufactured
SYNCHRONOUS
DRAM FAMILY
Device
Number
C=CMOS Family
Pin Count
60
3.3V, LVTTL INTERFACE
256Mb(8K Refresh)
4 Banks
Special
Feature
Speed
6 ns
7 ns
8 ns
WBGA Component
Package for 0.17um only
L=Low Power
Component Rev Level A=0.17um
B=0.14um
V=LVTTL
V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002
7

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부품번호상세설명 및 기능제조사
V54C3256804VB

256Mbit SDRAM 3.3 VOLT/ TSOP II / SOC BGA / WBGA PACKAGE 16M X 16/ 32M X 8/ 64M X 4

Mosel Vitelic  Corp
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