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V58C2128 데이터시트 PDF




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부품번호 V58C2128 기능
기능 HIGH PERFORMANCE 2.5 VOLT 128 Mbit DDR SDRAM
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V58C2128 데이터시트, 핀배열, 회로
MOSEL VITELIC
V58C2128(804/404/164)S
HIGH PERFORMANCE
2.5 VOLT 128 Mbit DDR SDRAM
4 BANKS X 4Mbit X 8 (804)
4 BANKS X 2Mbit X 16 (164)
4 BANKS X 8Mbit X 4 (404)
Clock Cycle Time (tCK2)
Clock Cycle Time (tCK2.5)
System Frequency (fCK max)
6
DDR333B
7.5 ns
6 ns
167 MHz
7
DDR266A
7.5ns
7ns
143 MHz
PRELIMINARY
75
DDR266B
10 ns
7.5 ns
133 MHz
8
DDR200
10 ns
8 ns
125 MHz
Features
High speed data transfer rates with system
frequency up to 166 MHz
Data Mask for Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 2.5
Programmable Wrap Sequence: Sequential
or Interleave
Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
Automatic and Controlled Precharge Command
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 4096 cycles/64 ms
Available in 66-pin 400 mil TSOP
SSTL-2 Compatible I/Os
Double Data Rate (DDR)
Bidirectional Data Strobe (DQS) for input and
output data, active on both edges
On-Chip DLL aligns DQ and DQs transitions with
CK transitions
Differential clock inputs CK and CK
Power Supply 2.5V ± 0.2V
QFC options for FET control. x4 parts.
*Note: DDR 333B Supports PC2700 module with 2.5-3-3 timing
DDR 266A Supports PC2100 module with 2-3-3 timing
DDR 266B Supports PC2100 module with 2.5-3-3 timing
DDR 200 Supports PC1600 module with 2-2-2 timing
Description
The V58C2128(804/404/164)S is a four bank
DDR DRAM organized as 4 banks x 4Mbit x 8 (804),
4 banks x 2Mbit x 16 (404), or 4 banks x 8Mbit x 4
(164). The V58C2128(804/404/164)S achieves high
speed data transfer rates by employing a chip archi-
tecture that prefetches multiple bits and then syn-
chronizes the output data to a system clock.
All of the control, address, circuits are synchro-
nized with the positive edge of an externally sup-
plied clock. I/O transactions are ocurring on both
edges of DQS.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at a higher rate than is possible with standard
DRAMs. A sequential and gapless data rate is pos-
sible depending on burst length, CAS latency and
speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
JEDEC 66 TSOP II
CK Cycle Time (ns)
-6 -7 -75 -8
• • ••
Power
Std.
L
Temperature
Mark
Blank
V58C2128(804/404/164)S Rev.1.6 March 2002
1




V58C2128 pdf, 반도체, 판매, 대치품
MOSEL VITELIC
V58C2128(804/404/164)S
Block Diagram
16M x 8
Column Addresses
A0 - A9, AP, BA0, BA1
Row Addresses
A0 - A11, BA0, BA1
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Bank 0
4096 x 512
x 16 bit
Row decoder
Memory array
Bank 1
4096 x 512
x 16 bit
Row decoder
Memory array
Bank 2
4096 x 512
x 16 bit
Row decoder
Memory array
Bank 3
4096 x 512
x 16 bit
CK, CK
DQS
Input buffer Output buffer
DLL
Strobe
Gen.
DQ0-DQ7
Data Strobe
Control logic & timing generator
V58C2128(804/404/164)S Rev. 1.6 March 2002
4

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V58C2128 전자부품, 판매, 대치품
MOSEL VITELIC
V58C2128(804/404/164)S
Mode Register Set (MRS)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs
CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to
make DDR SDRAM useful for a variety of different applications. The default value of the mode register is not
defined, therefore the mode register must be written after EMRS setting for proper DDR SDRAM operation.
The mode register is written by asserting low on CS, RAS, CAS, WE and BA0 (The DDR SDRAM should be
in all bank precharge with CKE already high prior to writing into the mode register). The state of address pins
A0 ~ A11 in the same cycle as CS, RAS, CAS, WE and BA0 low is written in the mode register. Two clock
cycles are required to meet tMRD spec. The mode register contents can be changed using the same com-
mand and clock cycle requirements during operation as long as all banks are in the idle state. The mode reg-
ister is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode
uses A3, CAS latency (read latency from column address) uses A4 ~ A6. A7 is a Mosel Vitelic specific test
mode during production test. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Refer
to the table for specific codes for various burst length, addressing modes and CAS latencies.
1. MRS can be issued only at all banks precharge state.
2. Minimum tRP is required to issue MRS command.
BA1 BA 0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
0 MRS
RFU : Must be set "0"
QFC I/O DLL Extended Mode Register
0 MRS
RFU
DLL TM CAS Latency BT Burst Length
Mode Register
A8 DLL Reset A7 mode
0 No
0 Normal
1 Yes
1 Test
A3 Burst Type
0 Sequential
1 Interleave
CAS Latency
Burst Length
BA0
An ~ A0
0 (Existing)MRS Cycle
A6 A5 A4 Latency
0 0 0 Reserve
A2 A1 A0
1 Extended Funtions(EMRS)
0 0 1 Reserve
000
01 0
2
001
01 1
3
010
1 0 0 Reserve
011
* RFU(Reserved for future use)
should stay "0" during MRS
cycle.
10
11
11
1 Reserve
0 2.5
1 Reserve
100
101
110
111
A1 I/O Strength
0 Full
1 Half
A0 DLL Enable
0 Enable
1 Disable
Latency
Sequential Interleave
Reserve Reserve
22
44
88
Reserve Reserve
Reserve Reserve
Reserve Reserve
Reserve Reserve
A2 QFC Control
0 Disable
1 Enable
Mode Register Set
012345678
CK, CK
Command
Precharge
All Banks
tCK
tRP *2
*1
Mode
Register Set
tMRD
Any
Command
V58C2128(804/404/164)S Rev. 1.6 March 2002
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부품번호상세설명 및 기능제조사
V58C2128

HIGH PERFORMANCE 2.5 VOLT 128 Mbit DDR SDRAM

Mosel Vitelic  Corp
Mosel Vitelic Corp
V58C2128164S

HIGH PERFORMANCE 2.5 VOLT 128 Mbit DDR SDRAM

Mosel Vitelic  Corp
Mosel Vitelic Corp

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