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V58C2256804S 데이터시트 PDF




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기능 HIGH PERFORMANCE 2.5 VOLT 256 Mbit DDR SDRAM
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V58C2256804S 데이터시트, 핀배열, 회로
MOSEL VITELIC
V58C2256(804/404/164)S
HIGH PERFORMANCE
2.5 VOLT 256 Mbit DDR SDRAM
4 BANKS X 8Mbit X 8 (804)
4 BANKS X 4Mbit X 16 (164)
4 BANKS X 16Mbit X 4 (404)
Clock Cycle Time (tCK2)
Clock Cycle Time (tCK2.5)
System Frequency (fCK max)
6
DDR333B
7.5 ns
6 ns
166 MHz
7
DDR266A
7.5ns
7ns
143 MHz
PRELIMINARY
75
DDR266B
10 ns
7.5 ns
133 MHz
8
DDR200
10 ns
8 ns
125 MHz
Features
High speed data transfer rates with system
frequency up to 166 MHz
Data Mask for Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 2.5
Programmable Wrap Sequence: Sequential
or Interleave
Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
Automatic and Controlled Precharge Command
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 8192 cycles/64 ms
Available in 66-pin 400 mil TSOP or 60 Ball SOC
BGA
SSTL-2 Compatible I/Os
Double Data Rate (DDR)
Bidirectional Data Strobe (DQS) for input and
output data, active on both edges
On-Chip DLL aligns DQ and DQs transitions with
CK transitions
Differential clock inputs CK and CK
Power Supply 2.5V ± 0.2V
QFC options for FET control. x4 parts.
*Note: DDR 333B Supports PC2700 module with 2.5-3-3 timing
DDR 266A Supports PC2100 module with 2-2-2 timing
DDR 266B Supports PC2100 module with 2.5-3-3 timing
DDR 200 Supports PC1600 module with 2-2-2 timing
Description
The V58C2256(804/404/164)S is a four bank
DDR DRAM organized as 4 banks x 8Mbit x 8 (804),
4 banks x 4Mbit x 16 (164), or 4 banks x 16Mbit x 4
(404). The V58C2256(804/404/164)S achieves high
speed data transfer rates by employing a chip archi-
tecture that prefetches multiple bits and then syn-
chronizes the output data to a system clock.
All of the control, address, circuits are synchro-
nized with the positive edge of an externally sup-
plied clock. I/O transactions are ocurring on both
edges of DQS.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at a higher rate than is possible with standard
DRAMs. A sequential and gapless data rate is pos-
sible depending on burst length, CAS latency and
speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
JEDEC 66 TSOP II
60 SOC BGA
CK Cycle Time (ns)
-6 -7 -75 -8
• • ••
Power
Std.
L
Temperature
Mark
Blank
V58C2256(804/404/164)S Rev.1.4 October 2002
1




V58C2256804S pdf, 반도체, 판매, 대치품
MOSEL VITELIC
V58C2256(804/404/164)S
V 58 C
MOSEL VITELIC
MANUFACTURED
2 256(80/40/16) 4
DDR SDRAM
CMOS
2.5V
256Mb, 8K Refresh
x8, x4, x16
S X T XX
SPEED
COMPONENT
PACKAGE, T = TSOP S=SOC BGA
COMPONENT
REV LEVEL A=0.14u
SSTL
4 Banks
Block Diagram
Column address
counter
64M x 4
Column Addresses
A0 - A9, A11, AP, BA0, BA1
Row Addresses
A0 - A12, BA0, BA1
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Bank 0
8192 x 1024
x8
Row decoder
Memory array
Bank 1
8192 x 1024
x8
Row decoder
Memory array
Bank 2
8192 x 1024
x8
Row decoder
Memory array
Bank 3
8192 x 1024
x8
CK, CK
DQS
Input buffer Output buffer
DLL
Strobe
Gen.
DQ0-DQ3
Data Strobe
Control logic & timing generator
V58C2256(804/404/164)S Rev. 1.4 October 2002
4

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V58C2256804S 전자부품, 판매, 대치품
MOSEL VITELIC
V58C2256(804/404/164)S
Signal Pin Description
Pin
CK
CK
CKE
Type
Input
Input
CS Input
RAS, CAS Input
WE
DQS
Input/
Output
A0 - A12 Input
Signal Polarity
Function
Pulse
Positive The system clock input. All inputs except DQs and DMs are sampled on the rising edge
Edge of CK.
Level Active High Activates the CK signal when high and deactivates the CK signal when low, thereby ini-
tiates either the Power Down mode, or the Self Refresh mode.
Pulse
Active Low CS enables the command decoder when low and disables the command decoder when
high. When the command decoder is disabled, new commands are ignored but previous
operations continue.
Pulse Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
command to be executed by the SDRAM.
Pulse
Active High Active on both edges for data input and output.
Center aligned to input data
Edge aligned to output data
Level
— During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-An defines the column address (CA0-CAn)
when sampled at the rising clock edge.CAn depends on the SDRAM organization:
64M x 4 DDR CAn = CA9, A11
32M x 8 DDR CAn = CA9
16M x 16 DDR CAn = CA8
BA0,
BA1
DQx
DM,
LDM,
UDM
QFC
Input
Input/
Output
Input
Output
VDD, VSS Supply
VDDQ Supply
VSSQ
VREF Input
Level
In addition to the column address, A10(=AP) is used to invoke autoprecharge operation
at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and
BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1
to control which bank(s) to precharge. If A10 is high, all four banks will be precharged
simultaneously regardless of state of BA0 and BA1.
— Selects which bank is to be active.
Level
— Data Input/Output pins operate in the same manner as on conventional DRAMs.
Pulse
Active High In Write mode, DM has a latency of zero and operates as a word mask by allowing input
data to be written if it is low but blocks the write operation if is high for x 16 LDM
corresponds to data on DQ0-DQ7, UDM corresponds to data on DQ8-DQ15.
Level Active Low FET Control: Output during every read and write access. Can be used to control isolation
switches on modules.
Power and ground for the input buffers and the core logic.
— — Isolated power supply and ground for the output buffers to provide improved noise
immunity.
Level
— SSTL Reference Voltage for Inputs
V58C2256(804/404/164)S Rev. 1.4 October 2002
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V58C2256804S

HIGH PERFORMANCE 2.5 VOLT 256 Mbit DDR SDRAM

Mosel Vitelic  Corp
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