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V58C265804S 데이터시트 PDF




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부품번호 V58C265804S 기능
기능 HIGH PERFORMANCE 2.5 VOLT 8M X 8 DDR SDRAM 4 BANKS X 2Mbit X 8
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V58C265804S 데이터시트, 핀배열, 회로
MOSEL VITELIC
V58C265804S
HIGH PERFORMANCE
2.5 VOLT 8M X 8 DDR SDRAM
4 BANKS X 2Mbit X 8
PRELIMINARY
System Frequency (fCK)
Clock Cycle Time (tCK3)
Clock Cycle Time (tCK2.5)
Clock Cycle Time (tCK2)
6
166 MHz
6 ns
6.5 ns
7ns
7
143 MHz
7 ns
7.5 ns
8ns
8
125 MHz
8 ns
9 ns
10ns
Features
s 4 banks x 2Mbit x 8 organization
s High speed data transfer rates with system
frequency up to 166 MHz
s Data Mask for Write Control (DM)
s Four Banks controlled by BA0 & BA1
s Programmable CAS Latency: 2, 2.5, 3
s Programmable Wrap Sequence: Sequential
or Interleave
s Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
s Automatic and Controlled Precharge Command
s Suspend Mode and Power Down Mode
s Auto Refresh and Self Refresh
s Refresh Interval: 4096 cycles/64 ms
s Available in 66-pin 400 mil TSOP-II
s SSTL-2 Compatible I/Os
s Double Data Rate (DDR)
s Bidirectional Data Strobe (DQs) for input and
output data, active on both edges
s On-Chip DLL aligns DQ and DQs transitions with
CLK transitions
s Differential clock inputs CLK and CLK
s Power Supply 2.5V ± 0.2V
Description
The V58C265804S is a four bank DDR DRAM or-
ganized as 4 banks x 2Mbit x 8. The V58C265804S
achieves high speed data transfer rates by employ-
ing a chip architecture that prefetches multiple bits
and then synchronizes the output data to a system
clock
All of the control, address, circuits are synchro-
nized with the positive edge of an externally sup-
plied clock. I/O transactions are possible on both
edges of DQS.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at a higher rate than is possible with standard
DRAMs. A sequential and gapless data rate is pos-
sible depending on burst length, CAS latency and
speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0°C to 70 °C
Package Outline
JEDEC 66 TSOP II
CLK Cycle Time (ns)
–6 -7 -8
• ••
Power
Std.
L
Temperature
Mark
Blank
V58C265804S Rev. 1.3 January 2000
1




V58C265804S pdf, 반도체, 판매, 대치품
MOSEL VITELIC
V58C265804S
Signal Pin Description
Pin
CLK
CLK
CKE
Type
Input
Input
CS Input
RAS, CAS Input
WE
DQS
Input/
Output
A0 - A11 Input
Signal Polarity
Function
Pulse
Positive The system clock input. All inputs except DQs and DMs are sampled on the rising edge
Edge of CLK.
Level Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby
initiates either the Power Down mode, Suspend mode, or the Self Refresh mode.
Pulse
Active Low CS enables the command decoder when low and disables the command decoder when
high. When the command decoder is disabled, new commands are ignored but previous
operations continue.
Pulse Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
command to be executed by the SDRAM.
Pulse
Active High Active on both edges for data input and output.
Center aligned to input data
Edge aligned to output data
Level
— During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-An defines the column address (CA0-CAn)
when sampled at the rising clock edge.CAn depends from the SDRAM organization:
8M x 8 SDRAM CAn = CA8 (Page Length = 512 bits)
BA0,
BA1
DQx
DM
Input
Input/
Output
Input
VDD, VSS Supply
VDDQ Supply
VSSQ
VREF Input
Level
In addition to the column address, A10(=AP) is used to invoke autoprecharge operation
at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and
BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1
to control which bank(s) to precharge. If A10 is high, all four banks will be precharged
simultaneously regardless of state of BA0 and BA1.
— Selects which bank is to be active.
Level
— Data Input/Output pins operate in the same manner as on conventional DRAMs.
Pulse Active High In Write mode, DM has a latency of zero and operates as a word mask by allowing input
data to be written if it is low but blocks the write operation if is high.
Power and ground for the input buffers and the core logic.
— — Isolated power supply and ground for the output buffers to provide improved noise
immunity.
Level
— SSTL Reference Voltage for Inputs
V58C265804S Rev. 1.3 January 2000
4

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V58C265804S 전자부품, 판매, 대치품
MOSEL VITELIC
Mode Register Set Timing
T0
CK, CK
Command
T1
tCK
T2
T3
tRP
Pre- All
T4 T5
tMRD
MRS/EMRS
T6 T7
ANY
V58C265804S
T8 T9
Mode Register set (MRS) or Extended Mode Register Set (EMRS) can be issued only when all banks are in the idle state.
If a MRS command is issued to reset the DLL, then an additional 200 clocks must occur prior to issuing any new command
to allow time for the DLL to lock onto the clock.
Burst Mode Operation
Burst Mode Operation is used to provide a constant flow of data to memory locations (Write cycle), or from
memory locations (Read cycle). Two parameters define how the burst mode will operate: burst sequence and
burst length. These parameters are programmable and are determined by address bits A0—A3 during the
Mode Register Set command. Burst type defines the sequence in which the burst data will be delivered or
stored to the SDRAM. Two types of burst sequence are supported: sequential and interleave. The burst
length controls the number of bits that will be output after a Read command, or the number of bits to be input
after a Write command. The burst length can be programmed to values of 2, 4, or 8. See the Burst Length
and Sequence table below for programming information.
Burst Length and Sequence
Burst Length
2
4
8
Starting Length (A2, A1, A0)
xx0
xx1
x00
x01
x10
x11
000
001
010
011
100
101
110
111
Sequential Mode
0, 1
1, 0
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0,1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5, 6
7, 0, 1, 2, 3, 4, 5, 6
Interleave Mode
0, 1
1, 0
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
0,1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
V58C265804S Rev. 1.3 January 2000
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V58C265804S

HIGH PERFORMANCE 2.5 VOLT 8M X 8 DDR SDRAM 4 BANKS X 2Mbit X 8

Mosel Vitelic  Corp
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